Merge pull request #51 from slaclab/pre-release

Release Candidate v5.8.0
slaclab · Jun 14, 2023 · aa552a7 · aa552a7
2 parents a4d28e3 + 1c5c7e2
commit aa552a7
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Showing 4 changed files with 425 additions and 10 deletions.
diff --git a/.github/workflows/lcls2_pgp_ci.yml b/.github/workflows/lcls2_pgp_ci.yml
@@ -11,7 +11,6 @@
 # ----------------------------------------------------------------------------
 # The following environment variables are required for this process:
 # secrets.GH_TOKEN
-# secrets.CONDA_UPLOAD_TOKEN_DEV
 # secrets.CONDA_UPLOAD_TOKEN_TAG
 
 name: Repo Integration
@@ -80,7 +79,7 @@ jobs:
   conda_build:
     name: Anaconda Build
     needs: [test]
-    if: startsWith(github.ref, 'refs/tags/') || github.ref == 'refs/heads/pre-release'
+    if: startsWith(github.ref, 'refs/tags/')
     strategy:
       matrix:
         os:
@@ -114,16 +113,10 @@ jobs:
       - name: Get Image Information
         id: get_image_info
         env:
-          CONDA_UPLOAD_TOKEN_DEV: ${{ secrets.CONDA_UPLOAD_TOKEN_DEV }}
           CONDA_UPLOAD_TOKEN_TAG: ${{ secrets.CONDA_UPLOAD_TOKEN_TAG }}
           OS_NAME: ${{ matrix.os }}
         run: |
-          if [ ${GITHUB_REF} == "refs/heads/pre-release" ]
-          then
-              echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_DEV
-          else
-              echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_TAG
-          fi
+          echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_TAG
           echo ::set-output name=os::linux-64
 
       - name: Build And Upload

diff --git a/hardware/XilinxVariumC1100/rtl/C1100Hsio.vhd b/hardware/XilinxVariumC1100/rtl/C1100Hsio.vhd
@@ -296,7 +296,7 @@ begin
                pgpRxN          => qsfp0RxN(i),
                pgpTxP          => qsfp0TxP(i),
                pgpTxN          => qsfp0TxN(i),
-               pgpRefClk       => gtRefClk,
+               pgpRefClk       => qsfp0RefClk,
                -- Streaming Interface (axilClk domain)
                pgpIbMaster     => pgpIbMasters(i),
                pgpIbSlave      => pgpIbSlaves(i),

diff --git a/hardware/XilinxVariumC1100/xdc/Pgp2bTiming.xdc b/hardware/XilinxVariumC1100/xdc/Pgp2bTiming.xdc
@@ -0,0 +1,39 @@
+##############################################################################
+## This file is part of LCLS2 PGP Firmware Library'.
+## It is subject to the license terms in the LICENSE.txt file found in the 
+## top-level directory of this distribution and at: 
+##    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
+## No part of LCLS2 PGP Firmware Library', including this file, 
+## may be copied, modified, propagated, or distributed except according to 
+## the terms contained in the LICENSE.txt file.
+##############################################################################
+
+create_generated_clock -name pgp2bPhyRxClk0 [get_pins -hier -filter {name =~ */GEN_LANE[0].GEN_PGP2b.U_Lane/*/RXOUTCLK}] 
+create_generated_clock -name pgp2bPhyTxClk0 [get_pins -hier -filter {name =~ */GEN_LANE[0].GEN_PGP2b.U_Lane/*/TXOUTCLK}]      
+
+create_generated_clock -name pgp2bPhyRxClk1  [get_pins -hier -filter {name =~ */GEN_LANE[1].GEN_PGP2b.U_Lane/*/RXOUTCLK}] 
+create_generated_clock -name pgp2bPhyTxClk1  [get_pins -hier -filter {name =~ */GEN_LANE[1].GEN_PGP2b.U_Lane/*/TXOUTCLK}]      
+
+create_generated_clock -name pgp2bPhyRxClk2  [get_pins -hier -filter {name =~ */GEN_LANE[2].GEN_PGP2b.U_Lane/*/RXOUTCLK}] 
+create_generated_clock -name pgp2bPhyTxClk2  [get_pins -hier -filter {name =~ */GEN_LANE[2].GEN_PGP2b.U_Lane/*/TXOUTCLK}]      
+
+create_generated_clock -name pgp2bPhyRxClk3  [get_pins -hier -filter {name =~ */GEN_LANE[3].GEN_PGP2b.U_Lane/*/RXOUTCLK}] 
+create_generated_clock -name pgp2bPhyTxClk3  [get_pins -hier -filter {name =~ */GEN_LANE[3].GEN_PGP2b.U_Lane/*/TXOUTCLK}]      
+
+set_clock_groups -asynchronous \
+    -group [get_clocks -include_generated_clocks {pgp2bPhyRxClk0}] \
+    -group [get_clocks -include_generated_clocks {pgp2bPhyTxClk0}] 
+
+
+set_clock_groups -asynchronous \
+    -group [get_clocks -include_generated_clocks {pgp2bPhyRxClk1}] \
+    -group [get_clocks -include_generated_clocks {pgp2bPhyTxClk1}] 
+
+set_clock_groups -asynchronous \
+    -group [get_clocks -include_generated_clocks {pgp2bPhyRxClk2}] \
+    -group [get_clocks -include_generated_clocks {pgp2bPhyTxClk2}] 
+
+set_clock_groups -asynchronous \
+    -group [get_clocks -include_generated_clocks {pgp2bPhyRxClk3}] \
+    -group [get_clocks -include_generated_clocks {pgp2bPhyTxClk3}] 
+