Memory safe DMA API

[japaric]

This is a first draft on building memory safe DMA abstractions.

r? @rust-embedded/resources
cc @korken89 @jamesmunns

[korken89]

Great first go at it!

[adamgreig]

It's worth mentioning you also need a memory barrier (DMB/DSB) when using devices with caches such as Cortex-M7's DCACHE, since the main SRAM is in general not coherent between the CPU and DMA.

Edit: You could also use explicit cache management to only invalidate the buffer in question instead of the whole memory, but it requires more careful management.

[japaric]

@adamgreig added a note about caches

If there are no more questions or requests then I think we can land this first version of this chapter.

[rj-xy]

Good write-up - Thanks

[japaric]

bors r=adamgreig

[bors]

Build succeeded

• continuous-integration/travis-ci/push

[jettr]

If we have a 'static lifetime, do we still need to Pin the buffers? It seems like adding 'static lifetime solves the original problem of using stack-based buffers, which don't live long enough.

If you can provide an example of an issue that would occur when you only have 'static without Pin, I think that would help me understand better.

Thank you!

[thalesfragoso]

We recently discovered that not even 'static + Pin is enough, see #64, we are working on a new documentation for this, see https://github.com/ra-kete/dma-poc for more details.

[jettr]

Thank you for the response. The links where very helpful, and I think the new documentation is very clear