Revert "Fix and add unittests."

This reverts commit 0642a01.

.github/workflows/black.yaml

@@ -1,6 +1,6 @@
 name: black
 
-on: [pull_request, push]
+on: [pull_request]
 
 jobs:
   linter:

.github/workflows/flake8.yml

@@ -1,6 +1,6 @@
 name: flake8
 
-on: [pull_request, push]
+on: [pull_request]
 
 jobs:
   linter:

.github/workflows/reuse.yaml

@@ -1,6 +1,6 @@
 name: reuse
 
-on: [pull_request, push]
+on: [pull_request]
 
 jobs:
   linter:

LLVMImporter.py

@@ -51,7 +51,7 @@ class LLVMImporter:
     sub_instruction_names = list()
     sub_instructions = dict()
     hardware_regs = dict()
-    rzilcompiler = None
+    rzil_compiler = None
     edited_files: [str] = list()
 
     def __init__(self, build_json: bool, gen_rzil: bool, skip_pcpp: bool, rzil_compile: bool, test_mode=False):
@@ -202,7 +202,7 @@ def generate_hexagon_json(self):
 
     def setup_rzil_compiler(self):
         log("Init compiler")
-        self.rzilcompiler = Compiler(ArchEnum.HEXAGON)
+        self.rzil_compiler = Compiler(ArchEnum.HEXAGON)
         if not self.skip_pcpp:
             self.rzilcompiler.run_preprocessor()
 
@@ -352,8 +352,7 @@ def parse_instructions(self) -> None:
                 t.n = i
                 t.postfix = f"Succ. compiled: {compiled_insn}/{len(no_pseudo)}"
                 t.update()
-        if self.gen_rzil:
-            self.rzilcompiler.transformer.ext.report_missing_fcns()
+        self.rzilcompiler.transformer.ext.report_missing_fcns()
 
         log("Parsed {} normal instructions.".format(len(self.normal_instructions)))
         log("Parsed {} sub-instructions.".format(len(self.sub_instructions)))