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This repository has been archived by the owner on Mar 7, 2024. It is now read-only.

Issues: riscvarchive/riscv-state-enable

10 Open 1 Closed
10 Open 1 Closed
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Issues list

*stateen0[0] read-only zeros?
#14 opened Feb 1, 2024 by vernonpang
Stateen bits designated for custom use?
#13 opened Feb 1, 2023 by henry-hsieh
Advice about enabling all state is potentially harmful
#12 opened Sep 7, 2022 by jrtc27
Controlling access to floating point and vector state from machine mode
#11 opened Aug 2, 2022 by dramforever
Stateen controlling access to state
#10 opened Aug 1, 2022 by vernonpang
How h/stateen become read-only zero for zero bits in mstateen?
#9 opened Jul 2, 2022 by liweiwei90
22
Why is this extension called Smstateen?
#8 opened Jun 21, 2022 by lbmeng
1
Clarify traps when Zfinx implemented
#6 opened Jan 5, 2022 by JamesKenneyImperas
Proposed AIA bit allocations should not be in normative text for stateen spec
#5 opened Nov 14, 2021 by kasanovic
Unclear why policy is proposed for emulation of read-only sstateen.
#4 opened Nov 14, 2021 by kasanovic
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