Merge branch 'main' into main

arch/inst/A/lr.w.yaml

@@ -45,7 +45,8 @@ lr.w:
      Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
      LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
      with both bits clear, but may result in lower performance.
-  definedBy: A
+  definedBy:
+    anyOf: [A, Zalrsc]
   assembly: xd, xs1
   encoding:
     match: 00010--00000-----010-----0101111

arch/inst/A/sc.d.yaml

@@ -96,7 +96,8 @@ sc.d:
     Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
     LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
     with both bits clear, but may result in lower performance.
-  definedBy: A
+  definedBy:
+    anyOf: [A, Zalrsc]
   assembly: xd, xs2, xs1
   encoding:
     match: 00011------------011-----0101111

arch/inst/A/sc.w.yaml

@@ -102,7 +102,8 @@ sc.w:
     Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set.
     LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those
     with both bits clear, but may result in lower performance.
-  definedBy: A
+  definedBy:
+    anyOf: [A, Zalrsc]
   assembly: xd, xs2, xs1
   encoding:
     match: 00011------------010-----0101111

arch/inst/B/andn.yaml

@@ -6,7 +6,7 @@ andn:
     This instruction performs the bitwise logical AND operation between `rs1` and the
     bitwise inversion of `rs2`.
   definedBy:
-    anyOf: [B, Zbb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   encoding:
     match: 0100000----------111-----0110011

arch/inst/B/clmul.yaml

@@ -5,7 +5,7 @@ clmul:
   description: |
     `clmul` produces the lower half of the 2*XLEN carry-less product
   definedBy:
-    anyOf: [B, Zbc]
+    anyOf: [B, Zbc, Zbkc, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   encoding:
     match: 0000101----------001-----0110011

arch/inst/B/clmulh.yaml

@@ -5,7 +5,7 @@ clmulh:
   description: |
     `clmulh` produces the upper half of the 2*XLEN carry-less product
   definedBy:
-    anyOf: [B, Zbc]
+    anyOf: [B, Zbc, Zbkc, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   encoding:
     match: 0000101----------011-----0110011

arch/inst/B/orn.yaml

@@ -5,7 +5,7 @@ orn:
   description: |
     This instruction performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.
   definedBy:
-    anyOf: [B, Zbb, Zbkb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   encoding:
     match: 0100000----------110-----0110011

arch/inst/B/rol.yaml

@@ -5,7 +5,7 @@ rol:
   description: |
     This instruction performs a rotate left of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
   definedBy:
-    anyOf: [B, Zbb, Zbkb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   encoding:
     match: 0110000----------001-----0110011

arch/inst/B/rolw.yaml

@@ -6,7 +6,7 @@ rolw:
     This instruction performs a rotate left of the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.
     The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.
   definedBy:
-    anyOf: [B, Zbb, Zbkb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   base: 64
   encoding:

arch/inst/B/ror.yaml

@@ -5,7 +5,7 @@ ror:
   description: |
     This instruction performs a rotate right of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
   definedBy:
-    anyOf: [B, Zbb, Zbkb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   encoding:
     match: 0110000----------101-----0110011

arch/inst/B/rori.yaml

@@ -6,7 +6,7 @@ rori:
     This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.
     For RV32, the encodings corresponding to shamt[5]=1 are reserved.
   definedBy:
-    anyOf: [B, Zbb, Zbkb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, shamt
   encoding:
     RV32:

arch/inst/B/roriw.yaml

@@ -7,7 +7,7 @@ roriw:
     the least-significant log2(XLEN) bits of shamt. The resulting word value is sign-extended by
     copying bit 31 to all of the more-significant bits.
   definedBy:
-    anyOf: [B, Zbb, Zbkb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, shamt
   base: 64
   encoding:

arch/inst/B/rorw.yaml

@@ -7,7 +7,7 @@ rorw:
     least-significant 5 bits of rs2. The resultant word is sign-extended by copying bit 31 to all
     of the more-significant bits.
   definedBy:
-    anyOf: [B, Zbb, Zbkb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   base: 64
   encoding:

arch/inst/B/xnor.yaml

@@ -5,7 +5,7 @@ xnor:
   description: |
     This instruction performs the bit-wise exclusive-NOR operation on rs1 and rs2.
   definedBy:
-    anyOf: [B, Zbb, Zbkb]
+    anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
   assembly: xd, xs1, xs2
   encoding:
     match: 0100000----------100-----0110011

arch/inst/B/zext.h.yaml

@@ -10,7 +10,7 @@ zext.h:
     The *zext.h* instruction is a pseudo-op for `pack` when `Zbkb` is implemented and XLEN == 32.
 
     [NOTE]
-    The *zext.h* instruction is a pseduo-op for `packw` when `Zbkb` is implmeneted and XLEN == 64.
+    The *zext.h* instruction is a pseudo-op for `packw` when `Zbkb` is implemented and XLEN == 64.
   definedBy:
     anyOf: [B, Zbb]
   encoding:
@@ -28,7 +28,8 @@ zext.h:
         location: 19-15
       - name: rd
         location: 11-7
-  excludedBy: Zbkb  # zext.h is a pseduo-op for pack/packw when Zbkb is implemented 
+  excludedBy: 
+    anyOf: [Zk, Zkn, Zks, Zbkb]  # zext.h instruction is a pseudo-op for `packw` when `Zbkb` is implemented 
   assembly: xd, xs1
   access:
     s: always

arch/inst/Zimop/mop.r.n.yaml

@@ -0,0 +1,94 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+mop.r.n:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: Zimop
+  assembly: mop_r_t_30, mop_r_t_27_26, mop_r_t_21_20, xd, xs1
+  encoding:
+    match: 1-00--0111-------100-----1110011
+    variables:
+    - name: mop_r_t_30
+      location: 30-30
+    - name: mop_r_t_27_26
+      location: 27-26
+    - name: mop_r_t_21_20
+      location: 21-20
+    - name: rs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: false
+  pseudoinstructions:
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0)
+    to: mop.r.0
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0)
+    to: mop.r.1
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0)
+    to: mop.r.2
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0)
+    to: mop.r.3
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1)
+    to: mop.r.4
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1)
+    to: mop.r.5
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1)
+    to: mop.r.6
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1)
+    to: mop.r.7
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2)
+    to: mop.r.8
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2)
+    to: mop.r.9
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2)
+    to: mop.r.10
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2)
+    to: mop.r.11
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3)
+    to: mop.r.12
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3)
+    to: mop.r.13
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3)
+    to: mop.r.14
+  - when: (mop_r_t_30 == 0x0) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3)
+    to: mop.r.15
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x0)
+    to: mop.r.16
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x0)
+    to: mop.r.17
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x0)
+    to: mop.r.18
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x0)
+    to: mop.r.19
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x1)
+    to: mop.r.20
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x1)
+    to: mop.r.21
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x1)
+    to: mop.r.22
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x1)
+    to: mop.r.23
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x2)
+    to: mop.r.24
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x2)
+    to: mop.r.25
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x2)
+    to: mop.r.26
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x2)
+    to: mop.r.27
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x0) && (mop_r_t_27_26 == 0x3)
+    to: mop.r.28
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x1) && (mop_r_t_27_26 == 0x3)
+    to: mop.r.29
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x2) && (mop_r_t_27_26 == 0x3)
+    to: mop.r.30
+  - when: (mop_r_t_30 == 0x1) && (mop_r_t_21_20 == 0x3) && (mop_r_t_27_26 == 0x3)
+    to: mop.r.31
+  operation(): |
+      

arch/inst/Zimop/mop.rr.n.yaml

@@ -0,0 +1,46 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+mop.rr.n:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: Zimop
+  assembly: mop_rr_t_30, mop_rr_t_27_26, xd, xs1, xs2
+  encoding:
+    match: 1-00--1----------100-----1110011
+    variables:
+    - name: mop_rr_t_30
+      location: 30-30
+    - name: mop_rr_t_27_26
+      location: 27-26
+    - name: rs2
+      location: 24-20
+    - name: rs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: false
+  pseudoinstructions:
+  - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x0)
+    to: mop.rr.0
+  - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x1)
+    to: mop.rr.1
+  - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x2)
+    to: mop.rr.2
+  - when: (mop_rr_t_30 == 0x0) && (mop_rr_t_27_26 == 0x3)
+    to: mop.rr.3
+  - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x0)
+    to: mop.rr.4
+  - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x1)
+    to: mop.rr.5
+  - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x2)
+    to: mop.rr.6
+  - when: (mop_rr_t_30 == 0x1) && (mop_rr_t_27_26 == 0x3)
+    to: mop.rr.7
+  operation(): |
+      

arch/inst/Zk/aes32dsi.yaml

@@ -0,0 +1,29 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+aes32dsi:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy:
+    anyOf: [Zk, Zkn, Zknd]
+  base: 32
+  assembly: xd, xs1, xs2, bs
+  encoding:
+    match: --10101----------000-----0110011
+    variables:
+    - name: bs
+      location: 31-30
+    - name: rs2
+      location: 24-20
+    - name: rs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+      

arch/inst/Zk/aes32dsmi.yaml

@@ -0,0 +1,29 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+aes32dsmi:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy:
+    anyOf: [Zk, Zkn, Zknd]
+  base: 32
+  assembly: xd, xs1, xs2, bs
+  encoding:
+    match: --10111----------000-----0110011
+    variables:
+    - name: bs
+      location: 31-30
+    - name: rs2
+      location: 24-20
+    - name: rs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+      

arch/inst/Zk/aes32esi.yaml

@@ -0,0 +1,29 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+aes32esi:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy:
+    anyOf: [Zk, Zkn, Zkne]
+  base: 32
+  assembly: xd, xs1, xs2, bs
+  encoding:
+    match: --10001----------000-----0110011
+    variables:
+    - name: bs
+      location: 31-30
+    - name: rs2
+      location: 24-20
+    - name: rs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+