Merge branch 'crd-james' of https://github.com/riscv-software-src/ris…

…cv-unified-db into crd-james

Gemfile

@@ -23,4 +23,5 @@ group :development do
   gem "solargraph"
   gem 'rubocop-minitest'
   gem 'ruby-prof'
+  gem "ruby-prof-flamegraph"
 end

Gemfile.lock

@@ -107,7 +107,9 @@ GEM
     rubocop-minitest (0.35.1)
       rubocop (>= 1.61, < 2.0)
       rubocop-ast (>= 1.31.1, < 2.0)
-    ruby-prof (1.7.0)
+    ruby-prof (0.18.0)
+    ruby-prof-flamegraph (0.3.0)
+      ruby-prof (~> 0.13)
     ruby-progressbar (1.13.0)
     ruby-rc4 (0.1.5)
     simpleidn (0.2.3)
@@ -152,6 +154,7 @@ DEPENDENCIES
   rouge
   rubocop-minitest
   ruby-prof
+  ruby-prof-flamegraph
   ruby-progressbar (~> 1.13)
   solargraph
   treetop (= 1.6.12)

Rakefile

@@ -1,5 +1,7 @@
 # frozen_string_literal: true
 
+require "etc"
+
 $root = Pathname.new(__FILE__).dirname.realpath
 $lib = $root / "lib"
 
@@ -82,45 +84,84 @@ namespace :validate do
     end
     puts "All files validate against their schema"  
   end
-  task idl: "gen:arch"  do
-    puts "Type checking IDL code..."
-    arch_def = arch_def_for("_")
-    progressbar = ProgressBar.create(title: "Instructions", total: arch_def.instructions.size)
-    arch_def.instructions.each do |inst|
-      progressbar.increment
-      inst.type_checked_operation_ast(arch_def.idl_compiler, arch_def.sym_table_32, 32) if inst.rv32?
-      inst.type_checked_operation_ast(arch_def.idl_compiler, arch_def.sym_table_64, 64) if inst.rv64?
-      # also need to check for an RV64 machine running with effective XLEN of 32
-      inst.type_checked_operation_ast(arch_def.idl_compiler, arch_def.sym_table_64, 32) if inst.rv64? && inst.rv32?
-    end
-    progressbar = ProgressBar.create(title: "CSRs", total: arch_def.csrs.size)
-    arch_def.csrs.each do |csr|
-      progressbar.increment
-      if csr.has_custom_sw_read?
-        csr.type_checked_sw_read_ast(arch_def.sym_table_32) if csr.defined_in_base32?
-        csr.type_checked_sw_read_ast(arch_def.sym_table_64) if csr.defined_in_base64?
-      end
-      csr.fields.each do |field|
-        unless field.type_ast(arch_def.idl_compiler).nil?
-          field.type_checked_type_ast(arch_def.sym_table_32) if csr.defined_in_base32? && field.defined_in_base32?
-          field.type_checked_type_ast(arch_def.sym_table_64) if csr.defined_in_base64? && field.defined_in_base64?
-        end
-        unless field.reset_value_ast(arch_def.idl_compiler).nil?
-          field.type_checked_reset_value_ast(arch_def.sym_table_32) if csr.defined_in_base32? && field.defined_in_base32?
-          field.type_checked_reset_value_ast(arch_def.sym_table_64) if csr.defined_in_base64? && field.defined_in_base64?
-        end
-        unless field.sw_write_ast(arch_def.idl_compiler).nil?
-          field.type_checked_sw_write_ast(arch_def.sym_table_32, 32) if csr.defined_in_base32? && field.defined_in_base32?
-          field.type_checked_sw_write_ast(arch_def.sym_table_64, 64) if csr.defined_in_base64? && field.defined_in_base64?
-        end
-      end
-    end
-    progressbar = ProgressBar.create(title: "Functions", total: arch_def.functions.size)
-    arch_def.functions.each do |func|
-      progressbar.increment
-      func.type_check_body(arch_def.sym_table_32)
-      func.type_check_body(arch_def.sym_table_64)
-    end
+  task idl: ["gen:arch", "#{$root}/.stamps/arch-gen-_32.stamp", "#{$root}/.stamps/arch-gen-_64.stamp"]  do
+    print "Parsing IDL code for RV32..."
+    arch_def_32 = arch_def_for("_32")
+    puts "done"
+
+    arch_def_32.type_check
+
+    print "Parsing IDL code for RV64..."
+    arch_def_64 = arch_def_for("_64")
+    puts "done"
+
+    arch_def_64.type_check
+
+    # arch_def_64 = arch_def_for("_64")
+    # arch_def_64.type_check
+
+    # puts "Type checking IDL code..."
+    # progressbar = ProgressBar.create(title: "Instructions", total: arch_def_32.instructions.size + arch_def_64.instructions.size)
+    # arch_def_32.instructions.each do |inst|
+    #   progressbar.increment
+    #   inst.type_checked_operation_ast(arch_def_32.idl_compiler, arch_def_32.symtab, 32) if inst.rv32?
+    # end
+    # arch_def_64.instructions.each do |inst|
+    #   progressbar.increment
+    #   inst.type_checked_operation_ast(arch_def_64.idl_compiler, arch_def_64.symtab, 64) if inst.rv64?
+    #   # also need to check for an RV64 machine running with effective XLEN of 32
+    #   inst.type_checked_operation_ast(arch_def_64.idl_compiler, arch_def_64.symtab, 32) if inst.rv64? && inst.rv32?
+    # end
+
+    # progressbar = ProgressBar.create(title: "CSRs", total: arch_def_32.csrs.size + arch_def_64.csrs.size)
+    # arch_def_32.csrs.each do |csr|
+    #   progressbar.increment
+    #   profile = RubyProf::Profile.new
+    #   result = profile.profile do
+    #     if csr.has_custom_sw_read?
+    #       csr.type_checked_sw_read_ast(arch_def_32.symtab) if csr.defined_in_base32?
+    #     end
+    #     csr.fields.each do |field|
+    #       unless field.type_ast(arch_def_32.symtab).nil?
+    #         field.type_checked_type_ast(arch_def_32.symtab) if csr.defined_in_base32? && field.defined_in_base32?
+    #       end
+    #       unless field.reset_value_ast(arch_def_32.symtab).nil?
+    #         field.type_checked_reset_value_ast(arch_def_32.symtab) if csr.defined_in_base32? && field.defined_in_base32?
+    #       end
+    #       unless field.sw_write_ast(arch_def_32.symtab).nil?
+    #         field.type_checked_sw_write_ast(arch_def_32.symtab, 32) if csr.defined_in_base32? && field.defined_in_base32?
+    #       end
+    #     end
+    #   end
+    #   RubyProf::GraphHtmlPrinter.new(result).print(File.open("#{csr.name}-prof.html", "w+"), {})
+    # end
+    # arch_def_64.csrs.each do |csr|
+    #   progressbar.increment
+    #   if csr.has_custom_sw_read?
+    #     csr.type_checked_sw_read_ast(arch_def_64.symtab) if csr.defined_in_base64?
+    #   end
+    #   csr.fields.each do |field|
+    #     unless field.type_ast(arch_def_64.symtab).nil?
+    #       field.type_checked_type_ast(arch_def_64.symtab) if csr.defined_in_base64? && field.defined_in_base64?
+    #     end
+    #     unless field.reset_value_ast(arch_def_64.symtab).nil?
+    #       field.type_checked_reset_value_ast(arch_def_64.symtab) if csr.defined_in_base64? && field.defined_in_base64?
+    #     end
+    #     unless field.sw_write_ast(arch_def_64.symtab).nil?
+    #       field.type_checked_sw_write_ast(arch_def_64.symtab, 32) if csr.defined_in_base32? && field.defined_in_base32?
+    #       field.type_checked_sw_write_ast(arch_def_64.symtab, 64) if csr.defined_in_base64? && field.defined_in_base64?
+    #     end
+    #   end
+    # end
+    # progressbar = ProgressBar.create(title: "Functions", total: arch_def_32.functions.size + arch_def_64.functions.size)
+    # arch_def_32.functions.each do |func|
+    #   progressbar.increment
+    #   func.type_check(arch_def_32.symtab)
+    # end
+    # arch_def_64.functions.each do |func|
+    #   progressbar.increment
+    #   func.type_check(arch_def_64.symtab)
+    # end
     puts "All IDL passed type checking"
   end
 end

arch/csr/H/htinst.yaml

@@ -0,0 +1,42 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+htinst:
+  address: 0x64a
+  long_name: Hypervisor Trap Instruction Register
+  description: |
+    When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero,
+    provides information about the instruction that trapped, to assist software in handling the trap.
+    The values that may be written to mtinst on a trap are documented in TODO.
+
+    htinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap.
+  priv_mode: S
+  length: SXLEN
+  definedBy: H
+  fields:
+    VALUE:
+      location_rv64: 63-0
+      location_rv32: 31-0
+      type(): |
+        if (   (TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT != "always zero")
+            || (TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT != "always zero")
+            || (TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT != "always zero")
+            || (TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED != "always zero")
+            || (TINST_VALUE_ON_BREAKPOINT != "always zero")
+            || (TINST_VALUE_ON_VIRTUAL_INSTRUCTION != "always zero")
+            || (TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED != "always zero")
+            || (TINST_VALUE_ON_LOAD_ACCESS_FAULT != "always zero")
+            || (TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED != "always zero")
+            || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always_zero")
+            || (TINST_VALUE_ON_UCALL != "always zero")
+            || (TINST_VALUE_ON_SCALL != "always zero")
+            || (TINST_VALUE_ON_MCALL != "always zero")
+            || (TINST_VALUE_ON_VSCALL != "always zero")
+            || (TINST_VALUE_ON_LOAD_PAGE_FAULT  != "always zero")
+            || (TINST_VALUE_ON_STORE_AMO_PAGE_FAULT != "always zero")) {
+          return CsrFieldType::RWH;
+        } else {
+          return CsrFieldType::RO;
+        }
+      description: |
+        Exception-speicific information for a trap into HS-mode.
+      reset_value: UNDEFINED_LEGAL

arch/csr/H/htval.yaml

@@ -0,0 +1,34 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+htval:
+  address: 0x643
+  long_name: Hypervisor Trap Value Register
+  description: |
+    When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap.
+
+    When a guest-page-fault trap is taken into HS-mode, htval is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, htval is set to zero, but a future standard or extension may redefine htval's setting for other traps.
+
+    A guest-page fault may arise due to an implicit memory access during first-stage (VS-stage) address translation, in which case a guest physical address written to htval is that of the implicit memory access that faulted-for example, the address of a VS-level page table entry that could not be read. (The guest physical address corresponding to the original virtual address is unknown when VS-stage translation fails to complete.) Additional information is provided in CSR htinst to disambiguate such situations.
+
+    Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in htval corresponds to the faulting portion of the access as indicated by the virtual address in stval. For instruction guest-page faults on systems with variable-length instructions, a nonzero htval corresponds to the faulting portion of the instruction as indicated by the virtual address in stval.
+
+    htval is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.
+  priv_mode: M
+  length: MXLEN
+  definedBy: H
+  fields:
+    VALUE:
+      location_rv64: 63-0
+      location_rv32: 31-0
+      type(): |
+        if (REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT
+            || REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT
+            || REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT
+            || REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT) {
+          return CsrFieldType::RWH;
+        } else {
+          return CsrFieldType::RO;
+        }
+      description: |
+        Exception-speicific information for a trap into M-mode.
+      reset_value: UNDEFINED_LEGAL

arch/csr/H/mtinst.yaml

@@ -0,0 +1,42 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+mtinst:
+  address: 0x34a
+  long_name: Machine Trap Instruction Register
+  description: |
+    When a trap is taken into M-mode, mtinst is written with a value that, if nonzero,
+    provides information about the instruction that trapped, to assist software in handling the trap.
+    The values that may be written to mtinst on a trap are documented in TODO.
+
+    mtinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap.
+  priv_mode: M
+  length: MXLEN
+  definedBy: H
+  fields:
+    VALUE:
+      location_rv64: 63-0
+      location_rv32: 31-0
+      type(): |
+        if (   (TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT != "always zero")
+            || (TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT != "always zero")
+            || (TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT != "always zero")
+            || (TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED != "always zero")
+            || (TINST_VALUE_ON_BREAKPOINT != "always zero")
+            || (TINST_VALUE_ON_VIRTUAL_INSTRUCTION != "always zero")
+            || (TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED != "always zero")
+            || (TINST_VALUE_ON_LOAD_ACCESS_FAULT != "always zero")
+            || (TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED != "always zero")
+            || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always_zero")
+            || (TINST_VALUE_ON_UCALL != "always zero")
+            || (TINST_VALUE_ON_SCALL != "always zero")
+            || (TINST_VALUE_ON_MCALL != "always zero")
+            || (TINST_VALUE_ON_VSCALL != "always zero")
+            || (TINST_VALUE_ON_LOAD_PAGE_FAULT  != "always zero")
+            || (TINST_VALUE_ON_STORE_AMO_PAGE_FAULT != "always zero")) {
+          return CsrFieldType::RWH;
+        } else {
+          return CsrFieldType::RO;
+        }
+      description: |
+        Exception-speicific information for a trap into M-mode.
+      reset_value: UNDEFINED_LEGAL

arch/csr/H/mtval2.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+mtval2:
+  address: 0x34b
+  long_name: Machine Second Trap Value Register
+  description: |
+    When a trap is taken into M-mode from a virtual mode, mtval2 is written with additional exception-specific information,
+    alongside mtval, to assist software in handling the trap.
+
+    When a guest-page-fault trap is taken into M-mode, mtval2 is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, mtval2 is set to zero, but a future standard or extension may redefine mtval2's setting for other traps.
+
+    If a guest-page fault is due to an implicit memory access during first-stage (VS-stage) address translation, a guest physical address written to mtval2 is that of the implicit memory access that faulted. Additional information is provided in CSR mtinst to disambiguate such situations.
+
+    Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in mtval2 corresponds to the faulting portion of the access as indicated by the virtual address in mtval. For instruction guest-page faults on systems with variable-length instructions, a nonzero mtval2 corresponds to the faulting portion of the instruction as indicated by the virtual address in mtval.
+
+    mtval2 is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.
+  priv_mode: M
+  length: MXLEN
+  definedBy: H
+  fields:
+    VALUE:
+      location_rv64: 63-0
+      location_rv32: 31-0
+      type(): |
+        if (REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT
+            || REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT
+            || REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT
+            || REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT) {
+          return CsrFieldType::RWH;
+        } else {
+          return CsrFieldType::RO;
+        }
+      description: |
+        Exception-speicific information for a trap into M-mode.
+      reset_value: UNDEFINED_LEGAL

arch/csr/H/vsatp.yaml

@@ -1,4 +1,4 @@
-# yaml-language-server: $schema=../../schemas/csr_schema.json
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
 
 vsatp:
   address: 0x280
@@ -94,7 +94,7 @@ vsatp:
             return UNDEFINED_LEGAL_DETERMINISTIC;
           }
         } else {
-          XReg shamt = (CSR[mstatus].SXL == $bits(XRegWidth::XLEN64)) ? 16 : 9;
+          XReg shamt = ((XLEN == 32) || (CSR[mstatus].SXL == $bits(XRegWidth::XLEN32))) ? 9 : 16;
           XReg all_ones = ((1 << shamt) - 1);
           XReg largest_allowed_asid = (1 << shamt) - 1;
 

arch/csr/cycleh.yaml

@@ -27,7 +27,7 @@ cycleh:
   fields:
     COUNT:
       location: 31-0
-      alias: mcycleh.COUNT
+      alias: mcycleh.COUNT[63:32]
       description: Alias of `mcycleh.COUNT`.
       type: RO-H
       reset_value: UNDEFINED_LEGAL

arch/csr/misa.yaml

@@ -90,7 +90,7 @@ misa:
     G:
       location: 6
       description: |
-        Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, 'D'.
+        Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, `D`.
       type(): |
         if ((implemented?(ExtensionName::A) && MUTABLE_MISA_A) ||
             (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ||

arch/csr/satp.yaml

@@ -119,7 +119,7 @@ satp:
             return UNDEFINED_LEGAL_DETERMINISTIC;
           }
         } else {
-          XReg shamt = (CSR[mstatus].SXL == $bits(XRegWidth::XLEN64)) ? 16 : 9;
+          XReg shamt = (XLEN == 32 || (CSR[mstatus].SXL == $bits(XRegWidth::XLEN32))) ? 9 : 16;
           XReg all_ones = ((1 << shamt) - 1);
           XReg largest_allowed_asid = (1 << shamt) - 1;
 

arch/ext/Sm.yaml

@@ -41,11 +41,11 @@ Sm:
       page-based virtual memory, even if VM is not currently enabled.
     - Removed the N extension.
     - Defined the mandatory RV32-only CSR `mstatush`, which contains most of
-      the same fields as the upper 32 bits of RV64’s `mstatus`.
+      the same fields as the upper 32 bits of RV64's `mstatus`.
     - Defined the mandatory CSR `mconfigptr`, which if nonzero contains the
       address of a configuration data structure.
     - Defined optional `mseccfg` and `mseccfgh` CSRs, which control the
-      machine’s security configuration.
+      machine's security configuration.
     - Defined `menvcfg` CSR (and RV32-only `menvcfgh`), which control various characteristics
       of the execution environment.
     - Designated part of SYSTEM major opcode for custom use.