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3 slices, 6 tiles
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rejunity committed Apr 19, 2024
1 parent 22c40ed commit dc83231
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2 changes: 1 addition & 1 deletion info.yaml
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Expand Up @@ -8,7 +8,7 @@ project:
clock_hz: 48000000 # Clock frequency in Hz (or 0 if not applicable)

# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "8x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
tiles: "3x2" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

# Your top module name must start with "tt_um_". Make it unique by including your github username:
top_module: "tt_um_rejunity_1_58bit"
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2 changes: 1 addition & 1 deletion src/config.tcl
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Expand Up @@ -12,7 +12,7 @@

# PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302.
# Users have reported that values up to 0.8 worked well for them.
set ::env(PL_TARGET_DENSITY) 0.7
set ::env(PL_TARGET_DENSITY) 0.78

# CLOCK_PERIOD - Increase this in case you are getting setup time violations.
# The value is in nanoseconds, so 20ns == 50MHz.
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2 changes: 1 addition & 1 deletion src/config.v
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Expand Up @@ -3,6 +3,6 @@
* SPDX-License-Identifier: Apache-2.0
*/

`define COMPUTE_SLICES 6
`define COMPUTE_SLICES 3

`define default_netname none

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