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Original file line number | Diff line number | Diff line change |
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# Support for AMD Instinct™ MI Series Accelerators | ||
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qsim provides support for AMD Instinct accelerators. | ||
The implementation covers the native GPU support in qsim | ||
by utilizing [AMD HIP SDK](https://rocm.docs.amd.com/projects/HIP) | ||
(Heterogeneous-Compute Interface for Portability). | ||
The cuQuantum implementation is currently not covered. | ||
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## Building | ||
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Building qsim with support for AMD Instinct accelerators requires installation of | ||
[AMD ROCm™ Open Software Platform](https://www.amd.com/en/developer/resources/rocm-hub.html). | ||
Instructions for installing ROCm are available at https://rocm.docs.amd.com/. | ||
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To enable support for AMD GPUs, qsim needs to be built from sources. | ||
This can be done as follows: | ||
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``` | ||
conda env list | ||
conda create -y -n CirqDevEnv python=3 | ||
conda activate CirqDevEnv | ||
pip install pybind11 | ||
git clone https://github.com/quantumlib/qsim.git | ||
cd qsim | ||
make -j qsim # to build CPU qsim | ||
make -j qsim-hip # to build HIP qsim | ||
make -j pybind # to build Python bindings | ||
make -j cxx-tests # to build CPU tests | ||
make -j hip-tests # to build HIP tests | ||
pip install . | ||
``` | ||
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Note: To avoid problems when building qsim with support for AMD GPUs, | ||
make sure to use the latest version of CMake. | ||
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## Testing | ||
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### Simulator | ||
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To test the qsim simulator: | ||
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``` | ||
make run-cxx-tests # to run CPU tests | ||
make run-hip-tests # to run HIP tests | ||
``` | ||
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or | ||
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``` | ||
cd tests | ||
for file in *.x; do ./"$file"; done # to run all tests | ||
for file in *_hip_test.x; do ./"$file"; done # to run HIP tests only | ||
``` | ||
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### Python Bindings | ||
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To test the Python bindings: | ||
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``` | ||
make run-py-tests | ||
``` | ||
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or | ||
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``` | ||
cd qsimcirq_tests | ||
python3 -m pytest -v qsimcirq_test.py | ||
``` | ||
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## Using | ||
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Using qsim on AMD Instinct GPUs is identical to using it on NVIDIA GPUs. | ||
I.e., it is done by passing `use_gpu=True` and `gpu_mode=0` as `qsimcirq.QSimOptions`: | ||
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``` | ||
simulator = qsimcirq.QSimSimulator(qsim_options=qsimcirq.QSimOptions( | ||
use_gpu=True, | ||
gpu_mode=0, | ||
... | ||
)) | ||
``` | ||
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Note: `gpu_mode` has to be set to zero for AMD GPUs, as cuStateVec is not supported. |
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// Copyright 2023 Advanced Micro Devices, Inc. | ||
// | ||
// Licensed under the Apache License, Version 2.0 (the "License"); | ||
// you may not use this file except in compliance with the License. | ||
// You may obtain a copy of the License at | ||
// | ||
// http://www.apache.org/licenses/LICENSE-2.0 | ||
// | ||
// Unless required by applicable law or agreed to in writing, software | ||
// distributed under the License is distributed on an "AS IS" BASIS, | ||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
// See the License for the specific language governing permissions and | ||
// limitations under the License. | ||
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#ifndef SIMULATOR_CUDA2HIP_H_ | ||
#define SIMULATOR_CUDA2HIP_H_ | ||
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#define cublasCaxpy hipblasCaxpy | ||
#define cublasCdotc hipblasCdotc | ||
#define cublasCreate hipblasCreate | ||
#define cublasCscal hipblasCscal | ||
#define cublasCsscal hipblasCsscal | ||
#define cublasDestroy hipblasDestroy | ||
#define cublasDznrm2 hipblasDznrm2 | ||
#define cublasHandle_t hipblasHandle_t | ||
#define cublasScnrm2 hipblasScnrm2 | ||
#define CUBLAS_STATUS_SUCCESS HIPBLAS_STATUS_SUCCESS | ||
#define cublasStatus_t hipblasStatus_t | ||
#define cublasZaxpy hipblasZaxpy | ||
#define cublasZdotc hipblasZdotc | ||
#define cublasZdscal hipblasZdscal | ||
#define cublasZscal hipblasZscal | ||
#define cuCimagf hipCimagf | ||
#define cuCimag hipCimag | ||
#define cuComplex hipComplex | ||
#define cuCrealf hipCrealf | ||
#define cuCreal hipCreal | ||
#define CUDA_C_32F HIPBLAS_C_32F | ||
#define CUDA_C_64F HIPBLAS_C_64F | ||
#define cudaDeviceSynchronize hipDeviceSynchronize | ||
#define cudaError_t hipError_t | ||
#define cudaFree hipFree | ||
#define cudaGetErrorString hipGetErrorString | ||
#define cudaMalloc hipMalloc | ||
#define cudaMemcpyAsync hipMemcpyAsync | ||
#define cudaMemcpyDeviceToDevice hipMemcpyDeviceToDevice | ||
#define cudaMemcpyDeviceToHost hipMemcpyDeviceToHost | ||
#define cudaMemcpy hipMemcpy | ||
#define cudaMemcpyHostToDevice hipMemcpyHostToDevice | ||
#define cudaMemset hipMemset | ||
#define cudaPeekAtLastError hipPeekAtLastError | ||
#define cudaSuccess hipSuccess | ||
#define cuDoubleComplex hipDoubleComplex | ||
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template <typename T> | ||
__device__ __forceinline__ T __shfl_down_sync( | ||
unsigned mask, T var, unsigned int delta, int width = warpSize) { | ||
return __shfl_down(var, delta, width); | ||
} | ||
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#endif // SIMULATOR_CUDA2HIP_H_ |
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