detect Meteor Lake CPU model #247
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@xujuntwt95329 do we have a test plan for this one ? |
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@mingfeima Thanks for the suggestion! Test plan updated: Tested using Intel SDE: #!/bin/bash
bash scripts/local-build.sh
OPTIONS=()
PLATFORMS=()
OPTIONS+=(-quark); PLATFORMS+=("Quark")
OPTIONS+=(-p4); PLATFORMS+=("Pentium4")
OPTIONS+=(-p4p); PLATFORMS+=("Pentium4 Prescott")
OPTIONS+=(-mrm); PLATFORMS+=("Merom")
OPTIONS+=(-pnr); PLATFORMS+=("Penryn")
OPTIONS+=(-nhm); PLATFORMS+=("Nehalem")
OPTIONS+=(-wsm); PLATFORMS+=("Westmere")
OPTIONS+=(-snb); PLATFORMS+=("Sandy Bridge")
OPTIONS+=(-ivb); PLATFORMS+=("Ivy Bridge")
OPTIONS+=(-hsw); PLATFORMS+=("Haswell")
OPTIONS+=(-bdw); PLATFORMS+=("Broadwell")
OPTIONS+=(-slt); PLATFORMS+=("Saltwell")
OPTIONS+=(-slm); PLATFORMS+=("Silvermont")
OPTIONS+=(-glm); PLATFORMS+=("Goldmont")
OPTIONS+=(-glp); PLATFORMS+=("Goldmont Plus")
OPTIONS+=(-tnt); PLATFORMS+=("Tremont")
OPTIONS+=(-snr); PLATFORMS+=("Snow Ridge")
OPTIONS+=(-skl); PLATFORMS+=("Skylake")
OPTIONS+=(-cnl); PLATFORMS+=("Cannon Lake")
OPTIONS+=(-icl); PLATFORMS+=("Ice Lake")
OPTIONS+=(-skx); PLATFORMS+=("Skylake server")
OPTIONS+=(-clx); PLATFORMS+=("Cascade Lake")
OPTIONS+=(-cpx); PLATFORMS+=("Cooper Lake")
OPTIONS+=(-icx); PLATFORMS+=("Ice Lake server")
OPTIONS+=(-tgl); PLATFORMS+=("Tiger Lake")
OPTIONS+=(-adl); PLATFORMS+=("Alder Lake")
OPTIONS+=(-rpl); PLATFORMS+=("Raptor Lake")
OPTIONS+=(-spr); PLATFORMS+=("Sapphire Rapids")
OPTIONS+=(-gnr); PLATFORMS+=("Granite Rapids")
OPTIONS+=(-srf); PLATFORMS+=("Sierra Forest")
OPTIONS+=(-future); PLATFORMS+=("Future chip")
SDE_BIN="path/to/sde"
for I in "${!PLATFORMS[@]}"; do
echo "${PLATFORMS["${I}"]}"
"${SDE_BIN}" "${OPTIONS[$I]}" -- ./build/local/cpu-info | grep -A 1 Microarchitectures
done
# Don't use -mtl option of SDE, the cpuid returned in that is wrong. Below is the cpuid content
# from MTL
echo "
00000000 ******** => 00000023 756E6547 6C65746E 49656E69 #
00000001 ******** => 000A06A4 11800800 7FFAFBFF BFEBFBFF #
00000002 ******** => 00FEFF01 000000F0 00000000 00000000 #
00000003 ******** => 00000000 00000000 00000000 00000000 #
00000004 00000000 => FC004121 02C0003F 0000003F 00000000 #
00000004 00000001 => FC004122 03C0003F 0000003F 00000000 #
00000004 00000002 => FC01C143 03C0003F 000007FF 00000000 #
00000004 00000003 => FC0FC163 02C0003F 00007FFF 00000004 #
00000005 ******** => 00000040 00000040 00000003 11112020 #
00000006 ******** => 00DFCFF7 00000002 00000409 00010003 #
00000007 00000000 => 00000002 239C27EB 994007AC FC18C410 #
00000007 00000001 => 40400910 00000001 00000000 00040000 #
00000007 00000002 => 00000000 00000000 00000000 0000003F #
00000008 ******** => 00000000 00000000 00000000 00000000 #
00000009 ******** => 00000000 00000000 00000000 00000000 #
0000000A ******** => 07300805 00000000 00000007 00008603 #
0000000B 00000000 => 00000001 00000002 00000100 00000018 #
0000000B 00000001 => 00000007 00000016 00000201 00000011 #
0000000C ******** => 00000000 00000000 00000000 00000000 #
0000000D ******** => 00000207 00000340 00000A88 00000000 #
0000000E ******** => 00000000 00000000 00000000 00000000 #
0000000F ******** => 00000000 00000000 00000000 00000000 #
00000010 ******** => 00000000 00000000 00000000 00000000 #
00000011 ******** => 00000000 00000000 00000000 00000000 #
00000013 ******** => 00000000 00000000 00000000 00000000 #
00000014 00000000 => 00000001 0000005F 00000007 00000000 #
00000014 00000001 => 02490002 003F003F 00000000 00000000 #
00000015 ******** => 00000002 0000009C 0249F000 00000000 #
00000016 ******** => 00000BB8 000012C0 00000064 00000000 #
00000017 ******** => 00000000 00000000 00000000 00000000 #
00000018 ******** => 00000008 00000000 00000000 00000000 #
00000019 ******** => 00000000 00000000 00000000 00000000 #
0000001A ******** => 40000002 00000000 00000000 00000000 #
0000001B ******** => 00000000 00000000 00000000 00000000 #
0000001C ******** => 4000000B 00000007 00000007 00000000 #
0000001D ******** => 00000000 00000000 00000000 00000000 #
0000001E ******** => 00000000 00000000 00000000 00000000 #
0000001F ******** => 00000001 00000002 00000100 00000018 #
00000020 ******** => 00000000 00000001 00000000 00000000 #
00000021 ******** => 00000000 00000000 00000000 00000000 #
00000022 ******** => 00000000 00000000 00000000 00000000 #
00000023 ******** => 0000000B 00000000 00000000 00000000 #
80000000 ******** => 80000008 00000000 00000000 00000000 #
80000001 ******** => 00000000 00000000 00000121 2C100800 #
80000002 ******** => 65746E49 2952286C 726F4320 4D542865 #
80000003 ******** => 6C552029 20617274 35312037 00004835 #
80000004 ******** => 00000000 00000000 00000000 00000000 #
80000005 ******** => 00000000 00000000 00000000 00000000 #
80000006 ******** => 00000000 00000000 08007040 00000000 #
80000007 ******** => 00000000 00000000 00000000 00000100 #
80000008 ******** => 0000302E 00000000 00000000 00000000 #
" > mtl.def
echo "Meteor Lake"
"${SDE_BIN}" -cpuid_in mtl.def -- ./build/local/cpu-info | grep -A 1 MicroarchitecturesResult: |
fbarchard
reviewed
May 31, 2024
include/cpuinfo.h
Outdated
| @@ -386,6 +386,9 @@ enum cpuinfo_uarch { | |||
| /** Intel/Marvell XScale series. */ | |||
| cpuinfo_uarch_xscale = 0x00100600, | |||
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| /** Intel Meteor Lake microarchitecture (Core Ultra 1st gen) */ | |||
| cpuinfo_uarch_meteor_lake = 0x00100700, | |||
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2 things: move this after sunny_cove & consider using the P and E core microarchitectures
meteorlake is the SoC
redwood and crestmont are the microarchitectures
each core can have a different microarchitecture and in XNNPack we can have a different microkernel for each thread.
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Thanks for the suggestions!
I noticed both P and E cores of MTL have same model number. I'll find some other field inside cpuid to identify the P core and E cores
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Could you fill in all the microarchitectures? When I run sde, the following show unknown: Looking up the documentation on these: |
Sure, I'll add these microarchitectures. |
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You could start with just the P-Core uarch and add hybrid in a followup PR. |
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Tested using Intel SDE for MTL/RPL/ADL: Result: |
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@mingfeima @fbarchard If this kind of modification is acceptable, we will add more uarch as suggested by @fbarchard |
fbarchard
reviewed
Jul 3, 2024
include/cpuinfo.h
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| cpuinfo_uarch_cypress_cove = 0x0010020E, | ||
| /** Intel Golden Cove microarchitecture (Intel 7, Alder Lake P-Cores) */ | ||
| cpuinfo_uarch_golden_cove = 0x0010020F, | ||
| /** Intel Gracemont Cove microarchitecture (Intel 7, Alder/Raptor Lake E-Cores) */ |
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E-Core names end in 'mont'. Remove 'cove' which is the naming for P-Cores.
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Thanks @fbarchard, I removed 'cove' from the end of Gracemont and Crestmont.
mingfeima
approved these changes
Jul 9, 2024
jgong5
approved these changes
Jul 9, 2024
fbarchard
reviewed
Jul 9, 2024
src/x86/uarch.c
Outdated
| @@ -2,6 +2,12 @@ | |||
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| #include <cpuinfo.h> | |||
| #include <x86/api.h> | |||
| #include <x86/cpuid.h> | |||
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| CPUINFO_INTERNAL bool cpuinfo_x86_detect_pcores(){ | |||
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Will this work on pcore-only CPUs? I'm thinking the reverse logic should be used?
cpuinfo_x86_detect_hybrid_ecore(){
If the hybrid is not present, pcore should be assumed.
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Thank you, we have modified it to check whether it is a hybrid architecture.
CPUINFO_INTERNAL bool cpuinfo_x86_detect_hybrid_ecore(){
if (((cpuid(0x1A).eax >> 24) & 0xFFF) == 0x20) return true;
return false;
}
fbarchard
reviewed
Jul 9, 2024
src/x86/uarch.c
Outdated
| @@ -167,6 +173,26 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( | |||
| case 0x7D: // Ice Lake-Y | |||
| case 0x7E: // Ice Lake-U | |||
| return cpuinfo_uarch_sunny_cove; | |||
| case 0xA7: // Rocket Lake | |||
| return cpuinfo_uarch_cypress_cove; | |||
| case 0x9A: // Alder Lake | |||
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Alder Lake pcore can also have a model 0x97:
See Also this excerpt from https://stackoverflow.com/questions/69955410/how-to-detect-p-e-core-in-intel-alder-lake-cpu
The CPUID instruction gives information about the core, on which it is executed. It is different for P cores and E cores.
The CPUID on Alder Lake is family 6 model 0x9A for both cores when enabled. The CPUID is changed to family 6 model 0x97 when E cores are disabled and AVX512 is enabled.
CPUID leaf 7 EDX bit 15 indicates a hybrid design.
CPUID leaf 1A EAX bit 24-31 indicates the type of core, according to "Game Dev Guide for Alder Lake Performance Hybrid Architecture", https://www.intel.com/content/www/us/en/developer/articles/guide/alder-lake-developer-guide.html
See my discussion at https://www.agner.org/forum/viewtopic.php?f=1&t=79
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New model IDs have been added for Rocket, Alder, and Meteor Lake.
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Thanks for reviewing the PR, could you help have a look again? @fbarchard |
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This PR add support for detecting Intel Meteor Lake CPU through its
model numberandextended model.