v0.5.0

Added

• Hardware support for:
  • Vector single-width integer divide instructions (vdivu, vdiv, vremu, vrem)
  • Vector integer comparison instructions (vmseq, vmsne, vmsltu, vmslt, vmsleu, vmsle, vmsgtu, vmsgt)
• Runtime measurement functions
• Consistent mode which orders scalar and vector loads/stores.
  • Conservative ordering without address comparison
  • Consistent mode is enabled per default, can be disabled by clearing the LSB of CSR 0x702.

Fixed

• Ariane's accelerator dispatcher module was rewritten, fixing a bug where instructions would get skipped.
• The Vector Store unit takes the EEW of the source vector register into account to shuffle the elements before writing them to memory.

Changed

• Vector mask instructions (vmand, vmnand, vmandnot, vmxor, vmor, vmnor, vmornot, vmxnor) no longer require the non-compliant constraint that the vector length is divisible by eight.