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cva6: Bump (rebase)
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Signed-off-by: Nils Wistoff <[email protected]>
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@niwis @mp-17
niwis authored and mp-17 committed Nov 3, 2023
1 parent 650a2e9 commit b72dcce
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion hardware/deps/cva6
Submodule cva6 updated 75 files
+6 −0 .gitlab-ci/expected_synth.yml
+19 −0 .readthedocs.yaml
+4 −0 README.md
+9 −1 core/alu.sv
+3 −1 core/amo_buffer.sv
+1 −0 core/ariane_regfile.sv
+1 −0 core/ariane_regfile_ff.sv
+1 −0 core/ariane_regfile_fpga.sv
+1 −0 core/axi_shim.sv
+3 −1 core/branch_unit.sv
+3 −1 core/cache_subsystem/amo_alu.sv
+14 −13 core/cache_subsystem/axi_adapter.sv
+1 −0 core/cache_subsystem/cache_ctrl.sv
+1 −0 core/cache_subsystem/cva6_icache.sv
+3 −0 core/cache_subsystem/cva6_icache_axi_wrapper.sv
+3 −0 core/cache_subsystem/miss_handler.sv
+3 −0 core/cache_subsystem/std_cache_subsystem.sv
+4 −0 core/cache_subsystem/std_nbdcache.sv
+1 −0 core/cache_subsystem/tag_cmp.sv
+2 −0 core/cache_subsystem/wt_axi_adapter.sv
+5 −0 core/cache_subsystem/wt_cache_subsystem.sv
+5 −0 core/cache_subsystem/wt_dcache.sv
+1 −0 core/cache_subsystem/wt_dcache_ctrl.sv
+1 −0 core/cache_subsystem/wt_dcache_mem.sv
+1 −0 core/cache_subsystem/wt_dcache_missunit.sv
+5 −3 core/cache_subsystem/wt_dcache_wbuffer.sv
+2 −1 core/cache_subsystem/wt_l15_adapter.sv
+3 −2 core/commit_stage.sv
+6 −5 core/compressed_decoder.sv
+3 −1 core/controller.sv
+3 −1 core/csr_buffer.sv
+3 −2 core/csr_regfile.sv
+19 −5 core/cva6.sv
+3 −1 core/cvxif_fu.sv
+29 −8 core/decoder.sv
+17 −5 core/ex_stage.sv
+3 −1 core/fpu_wrap.sv
+7 −6 core/frontend/bht.sv
+3 −2 core/frontend/btb.sv
+4 −1 core/frontend/frontend.sv
+19 −17 core/frontend/instr_queue.sv
+3 −1 core/frontend/instr_scan.sv
+1 −0 core/frontend/ras.sv
+9 −3 core/id_stage.sv
+8 −0 core/include/ariane_pkg.sv
+3 −3 core/include/riscv_pkg.sv
+1 −1 core/include/std_cache_pkg.sv
+3 −1 core/instr_realign.sv
+6 −1 core/issue_read_operands.sv
+6 −1 core/issue_stage.sv
+10 −2 core/load_store_unit.sv
+1 −0 core/load_unit.sv
+3 −1 core/lsu_bypass.sv
+5 −0 core/mmu_sv32/cva6_mmu_sv32.sv
+7 −5 core/mmu_sv32/cva6_ptw_sv32.sv
+28 −27 core/mmu_sv32/cva6_shared_tlb_sv32.sv
+10 −9 core/mmu_sv32/cva6_tlb_sv32.sv
+8 −2 core/mmu_sv39/mmu.sv
+2 −0 core/mmu_sv39/ptw.sv
+6 −5 core/mmu_sv39/tlb.sv
+7 −2 core/mult.sv
+7 −1 core/multiplier.sv
+3 −2 core/perf_counters.sv
+1 −0 core/pmp/src/pmp.sv
+5 −4 core/pmp/src/pmp_entry.sv
+11 −9 core/re_name.sv
+2 −1 core/scoreboard.sv
+3 −2 core/serdiv.sv
+5 −3 core/store_buffer.sv
+9 −3 core/store_unit.sv
+70 −24 docs/01_cva6_user/PMA.rst
+2 −2 docs/01_cva6_user/ip-xact/cva6_csr.md
+2 −2 docs/01_cva6_user/ip-xact/cva6_csr.rst
+2 −2 docs/01_cva6_user/ip-xact/cva6_csr.xml
+2 −2 docs/01_cva6_user/ip-xact/cva6_csr.yaml

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