Merge branch 'apu2b-20160304-sd-a8' into apu2b-20160304

configs/pcengines.apu2.20160304.config

@@ -330,11 +330,11 @@ CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0x0
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=3
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=1
 # CONFIG_NO_POST is not set
 # CONFIG_CMOS_POST is not set
 # CONFIG_CONSOLE_POST is not set
@@ -391,7 +391,7 @@ CONFIG_PAYLOAD_SEABIOS=y
 CONFIG_SEABIOS_ELTAN=y
 CONFIG_SEABIOS_STABLE=y
 # CONFIG_SEABIOS_MASTER is not set
-CONFIG_ELTAN_SEABIOS_TAG="dc06fd2a7057e9a2f748cf6a9f8fb8d41a95097c"
+CONFIG_ELTAN_SEABIOS_TAG="ac6d3e213a3867bd586b62924b8255d57333e078"
 # CONFIG_SEABIOS_SERIAL_CONSOLE is not set
 # CONFIG_SKIP_PXE_LOAD is not set
 # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set

payloads/external/SeaBIOS/Makefile.inc

@@ -70,6 +70,8 @@ ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y)
 	echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config
 endif
 
+	echo "CONFIG_DEBUG_LEVEL=0" >> seabios/.config
+
 ifeq ($(CONFIG_SEABIOS_SERIAL_CONSOLE),y)
 	echo "CONFIG_SEABIOS_SERIAL_CONSOLE=y" >> seabios/.config
 	echo "CONFIG_DEBUG_LEVEL=0" >> seabios/.config

src/mainboard/pcengines/apu2/boot-menu-message

@@ -1 +1 @@
-PCengines Press F10 key now for boot menu:
+Press F10 key now for boot menu, N for PXE boot

src/mainboard/pcengines/apu2/bootorder_def

@@ -5,4 +5,4 @@
 /pci@i0cf8/*@14,7
 /pci@i0cf8/*@11/drive@0/disk@0
 /pci@i0cf8/*@11/drive@1/disk@0
-
+/rom@genroms/pxe.rom

src/mainboard/pcengines/apu2/bootorder_map

@@ -1,8 +1,8 @@
-a USB 1 SS
-b USB 2 SS
-c USB 1 HS
-d USB 2 HS
-e SDCARD
-f mSATA
-g SATA
-
+a USB 1 / USB 2 SS and HS
+a USB 1 / USB 2 SS and HS
+a USB 1 / USB 2 SS and HS
+a USB 1 / USB 2 SS and HS
+b SDCARD
+c mSATA
+d SATA
+e iPXE

src/mainboard/pcengines/apu2/mainboard.c

@@ -46,6 +46,8 @@
 #include <cbfs_core.h>
 #include <spd_cache.h>
 
+static bool check_console(void);
+
 /**********************************************
  * enable the dedicated function in mainboard.
  **********************************************/
@@ -54,10 +56,14 @@ static void mainboard_enable(device_t dev)
 {
 	struct device *sio_dev;
 
+	bool scon = check_console();
 	setup_bsp_ramtop();
 	u32 TOM1 = bsp_topmem() / (1024 *1024);	// Tom1 in Mbyte
 	u32 TOM2 = ( bsp_topmem2() / (1024 *1024)) - 4 * 1024;	// Tom2 in Mbyte
-	printk(BIOS_ERR, "%d MB", TOM1+TOM2);
+	if (scon) {
+		printk(BIOS_ALERT, CONFIG_MAINBOARD_PART_NUMBER "\n");
+		printk(BIOS_ALERT, "%d MB", TOM1+TOM2);
+	}
 
 	u8 spd_buffer[SPD_SIZE];
 	int	index = 0;
@@ -66,13 +72,15 @@ static void mainboard_enable(device_t dev)
 
 	if ( ReadFchGpio(APU2_SPD_STRAP0_GPIO) ) index |= BIT0;
 	if ( ReadFchGpio(APU2_SPD_STRAP1_GPIO) ) index |= BIT1;
-	
+
 	printk(BIOS_SPEW, "Reading SPD index %d to get ECC info \n", index);
 	if (read_spd_from_cbfs(spd_buffer, index) < 0)
 		spd_buffer[3]=3;	// Indicate no ECC
 
-	if ( spd_buffer[3] == 8 ) 	printk(BIOS_ERR, " ECC");
-	printk(BIOS_ERR, " DRAM\n\n");
+	if (scon) {
+		if ( spd_buffer[3] == 8 ) 	printk(BIOS_ALERT, " ECC");
+		printk(BIOS_ALERT, " DRAM\n\n");
+	}
 
 	//
 	// Enable the RTC output
@@ -249,7 +257,7 @@ static void mainboard_final(void *chip_info) {
 		//
 		// The console should be disabled
 		//
-		unsigned char data = 1;
+		unsigned char data = 0;
 
 		//
 		// Indicated to SeaBIOS it should display console output itself

src/southbridge/amd/pi/hudson/sd.c

@@ -31,27 +31,29 @@ static void sd_init(struct device *dev)
 
 	stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
 
-	struct southbridge_amd_pi_hudson_config *sd_chip =
-		(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);
+// Force to use SD host in 2.0 mode for APU2
+//	struct southbridge_amd_pi_hudson_config *sd_chip =
+//		(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);
 
-	if (sd_chip->sd_mode == 3) {	/* SD 3.0 mode */
-		pci_write_config32(dev, 0xA4, 0x31FEC8B2);
-		pci_write_config32(dev, 0xA8, 0x00002503);
-		pci_write_config32(dev, 0xB0, 0x02180C19);
-		pci_write_config32(dev, 0xD0, 0x0000078B);
-	}
-	else {				/* SD 2.0 mode */
+//	if (sd_chip->sd_mode == 3) {	/* SD 3.0 mode */
+//		pci_write_config32(dev, 0xA4, 0x31FEC8B2);
+//		pci_write_config32(dev, 0xA8, 0x00002503);
+//		pci_write_config32(dev, 0xB0, 0x02180C19);
+//		pci_write_config32(dev, 0xD0, 0x0000078B);
+//	}
+//	else {				/* SD 2.0 mode */
 		if ((stepping & 0x0000000F) == 0) {	/* Stepping A0 */
-			pci_write_config32(dev, 0xA4, 0x31DE32B2);
-			pci_write_config32(dev, 0xB0, 0x01180C19);
+			pci_write_config32(dev, 0xA4, 0x21DE32B2);
+			pci_write_config32(dev, 0xB0, 0x01180C01);
 			pci_write_config32(dev, 0xD0, 0x0000058B);
 		}
 		else {					/* Stepping >= A1 */
-			pci_write_config32(dev, 0xA4, 0x31FE3FB2);
-			pci_write_config32(dev, 0xB0, 0x01180C19);
+			pci_write_config32(dev, 0xA4, 0x21FE32B2);
+			pci_write_config32(dev, 0xA8, 0x00000070);
+			pci_write_config32(dev, 0xB0, 0x01180C01);
 			pci_write_config32(dev, 0xD0, 0x0000078B);
 		}
-	}
+//	}
 }
 
 static struct device_operations sd_ops = {