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config_pkg: fix HPDCache related parameter #2731
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✔️ successful run, report available here. |
@yanicasa Can you review this PR, it is close to your current activity... Thanks |
As a side note, we could opt to set |
or (of course) @cfuguet |
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Yes. This was a bug. FYI, I'm adding a specific assertion to check this parameter in the HPDcache.
One comment: non power of two values will cause a port width mismatch in a decoder inside the HPDCache on the |
This PR fixes one configuration, bu what about the other configurations. Maybe the fix should be applied on all configurations? |
It is my understanding this issue arises with the WB HPDCache only. The parameter serves different purposes depending on the cache policy. Are there other targets with the WB HPDCache? |
Thanks ! |
Yes, I confirm that it is the only configuration concerned. |
The AXI AW channel in the HPDcache is shared by three components:
The ID for each transaction is generated based on its source as follows:
{1'b0, write_buffer_entry_index}
{1'b1, flush_controller_index}
'1
To distinguish between flush transactions and uncached transactions, the flush transaction ID must include at least one 0.
Currently, the AXI ID is limited to 4 bits, while the flush controller supports 8 entries. As a result, when a transaction is sent from the 8th entry of the flush controller, all bits of the ID are set to 1. This causes the HPDcache to misroute the response to the uncached controller instead of the flush controller.
The parameter
CVA6ConfigWtDcacheWbufDepth
is used in the WB cache to set the number of flush entries. To avoid modifying the ID width, the number of flush entries must be less than 8. Non-power-of-two values are supported.