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Fix decoding of CLRI, BINVI, BSETI, BEXTI and RORI where bit 25 is reserved in RV32 Fix #2280 #2728
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JeanRochCoulon
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ThalesSiliconSecurity:dev/b-decoder
Jan 22, 2025
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Fix decoding of CLRI, BINVI, BSETI, BEXTI and RORI where bit 25 is reserved in RV32 Fix #2280 #2728
JeanRochCoulon
merged 3 commits into
openhwgroup:master
from
ThalesSiliconSecurity:dev/b-decoder
Jan 22, 2025
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core/decoder.sv
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else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b010_010) instruction_o.op = ariane_pkg::BEXTI; | ||
else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b010_0100) instruction_o.op = ariane_pkg::BEXTI; | ||
else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b011_000) instruction_o.op = ariane_pkg::RORI; | ||
else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b011_0000) instruction_o.op = ariane_pkg::RORI; |
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[verible-verilog-format] reported by reviewdog 🐶
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else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b010_010) instruction_o.op = ariane_pkg::BEXTI; | |
else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b010_0100) instruction_o.op = ariane_pkg::BEXTI; | |
else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b011_000) instruction_o.op = ariane_pkg::RORI; | |
else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b011_0000) instruction_o.op = ariane_pkg::RORI; | |
else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b010_010) | |
instruction_o.op = ariane_pkg::BEXTI; | |
else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b010_0100) | |
instruction_o.op = ariane_pkg::BEXTI; | |
else if (CVA6Cfg.IS_XLEN64 && instr.instr[31:26] == 6'b011_000) | |
instruction_o.op = ariane_pkg::RORI; | |
else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b011_0000) | |
instruction_o.op = ariane_pkg::RORI; |
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Fix decoding of some bitmanip instruction where decoding differs between rv32 and rv64