ym3438: fix ssg-eg logic & minor changes

nukeykt · Jul 31, 2023 · be77739 · be77739
1 parent f99da78
commit be77739
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Showing 5 changed files with 31 additions and 6 deletions.
diff --git a/ym3438_ch.v b/ym3438_ch.v
@@ -94,7 +94,7 @@ module ym3438_ch
 
 	wire [8:0] ch_value_lock_o;
 
-	ym_slatch #(.DATA_WIDTH(9)) ch_value_lock
+	ym_slatch2 #(.DATA_WIDTH(9)) ch_value_lock
 		(
 		.MCLK(MCLK),
 		.en(~ch_lock),

diff --git a/ym3438_eg.v b/ym3438_eg.v
@@ -195,7 +195,7 @@ module ym3438_eg
 
 	wire [1:0] eg_cnt_low_o;
 
-	ym_slatch #(.DATA_WIDTH(2)) eg_cnt_low
+	ym_slatch2 #(.DATA_WIDTH(2)) eg_cnt_low
 		(
 		.MCLK(MCLK),
 		.en(eg_cnt_ed_o),
@@ -217,7 +217,7 @@ module ym3438_eg
 
 	wire [3:0] eg_cnt_shift_o;
 
-	ym_slatch #(.DATA_WIDTH(4)) eg_cnt_shift
+	ym_slatch2 #(.DATA_WIDTH(4)) eg_cnt_shift
 		(
 		.MCLK(MCLK),
 		.en(eg_cnt_ed_o),
@@ -617,7 +617,7 @@ module ym3438_eg
 	assign ssg_toggle = ssg_enable & eg_level_sr_o1[9] & ssg_repeat;
 
 	assign ssg_inv_i = ssg_enable & okon_sr1_o
-		& ((eg_level_sr_o1[9] & ssg_type3) | ((eg_level_sr_o1[9] ^ ssg_inv_o) & ssg_type2));
+		& ((eg_level_sr_o1[9] & ssg_type3) | ((eg_level_sr_o1[9] & ssg_type2) ^ ssg_inv_o));
 
 	wire kon_toggle = kon_sr_o & ~okon_sr_o;
 	wire kon_toggle_off = ~kon_sr_o & okon_sr_o;

diff --git a/ym3438_lfo.v b/ym3438_lfo.v
@@ -102,7 +102,7 @@ module ym3438_lfo
 
 	wire [6:0] lfo_cnt_lock;
 
-	ym_slatch #(.DATA_WIDTH(7)) lfo_cnt_l
+	ym_slatch2 #(.DATA_WIDTH(7)) lfo_cnt_l
 		(
 		.MCLK(MCLK),
 		.en(lfo_cnt_load),

diff --git a/ym3438_regs.v b/ym3438_regs.v
@@ -498,7 +498,7 @@ module ym3438_reg_ctrl
 		.outp(load_ed_o)
 		);
 
-	ym_slatch #(.DATA_WIDTH(2)) pan_lock
+	ym_slatch2 #(.DATA_WIDTH(2)) pan_lock
 		(
 		.MCLK(MCLK),
 		.en(load_ed_o),

diff --git a/ym_lib.v b/ym_lib.v
@@ -353,6 +353,31 @@ module ym_slatch #(parameter DATA_WIDTH = 1)
 
 endmodule
 
+module ym_slatch2 #(parameter DATA_WIDTH = 1)
+	(
+	input MCLK,
+	input en,
+	input [DATA_WIDTH-1:0] inp,
+	output [DATA_WIDTH-1:0] val,
+	output [DATA_WIDTH-1:0] nval
+	);
+
+	reg [DATA_WIDTH-1:0] mem = {DATA_WIDTH{1'h0}};
+
+	wire [DATA_WIDTH-1:0] mem_assign = en ? inp : mem;
+
+	always @(posedge MCLK)
+	begin
+		mem <= mem_assign;
+	end
+
+	//assign val = mem_assign;
+	//assign nval = ~mem_assign;
+	assign val = mem;
+	assign nval = ~mem;
+
+endmodule
+
 /*module ym_slatch_t #(parameter DATA_WIDTH = 1)
 	(
 	input MCLK,