beginning sd integration

Nexys4Game/src/hdl/CL_block.v

@@ -1,17 +1,103 @@
 module CL_block(
     input clk, //100mhz clk
+    input clk25, //25mhz clk
     input pause_SW, //Debounced switch input for pause
     input reset_button, //Debounced button for reset
+    input SD_CD,
 
+    inout [3:0] SD_DAT,
+
+    output SD_RESET,
+    output SD_SCK,
+    output SD_CMD,
     output reset, //status signal for reset
     output pause, //status signal for game-pause
     output song_time //current song_time
     );
 
+    //////////////////////////////////////////////////////////////////////////////////
+    //  SD stuff
+
+    wire rst = reset;
+    wire spiClk;
+    wire spiMiso;
+    wire spiMosi;
+    wire spiCS;
+
+    // MicroSD SPI/SD Mode/Nexys 4
+    // 1: Unused / DAT2 / SD_DAT[2]
+    // 2: CS / DAT3 / SD_DAT[3]
+    // 3: MOSI / CMD / SD_CMD
+    // 4: VDD / VDD / ~SD_RESET
+    // 5: SCLK / SCLK / SD_SCK
+    // 6: GND / GND / - 
+    // 7: MISO / DAT0 / SD_DAT[0]
+    // 8: UNUSED / DAT1 / SD_DAT[1]
+    assign SD_DAT[2] = 1;
+    assign SD_DAT[3] = spiCS;
+    assign SD_CMD = spiMosi;
+    assign SD_RESET = 0;
+    assign SD_SCK = spiClk;
+    assign spiMiso = SD_DAT[0];
+    assign SD_DAT[1] = 1;
+
+    reg rd = 0;
+    reg wr = 0;
+    reg [7:0] din = 0;
+    wire [7:0] dout;
+    wire byte_available;
+    wire ready;
+    wire ready_for_next_byte;
+    reg [31:0] adr = 32'h00_00_00_00;
+
+    reg [15:0] bytes = 0;
+    reg [1:0] bytes_read = 0;
+
+    wire [4:0] state;
+
+    parameter STATE_INIT = 0;
+    parameter STATE_START = 1;
+    parameter STATE_WRITE = 2;
+    parameter STATE_READ = 3;
+    reg [1:0] test_state = STATE_INIT; 
+    //assign LED = {state, ready, test_state, bytes[15:8]};  
+
+    sd_controller sd_controller( //these connections are not in io order
+        .cs(spiCS), // Connect to SD_DAT[3].
+        .mosi(spiMosi), // Connect to SD_CMD.
+        .miso(spiMiso), // Connect to SD_DAT[0].
+        .sclk(spiClk), // Connect to SD_SCK.
+                            // For SPI mode, SD_DAT[2] and SD_DAT[1] should be held HIGH. 
+                            // SD_RESET should be held LOW.
+        .rd(rd), // Read-enable. When [ready] is HIGH, asseting [rd] will 
+                            // begin a 512-byte READ operation at [address]. 
+                            // [byte_available] will transition HIGH as a new byte has been
+                            // read from the SD card. The byte is presented on [dout].
+        .dout(dout), // Data output for READ operation.
+        .byte_available(byte_available), // A new byte has been presented on [dout].
+        .wr(wr), // Write-enable. When [ready] is HIGH, asserting [wr] will
+                            // begin a 512-byte WRITE operation at [address].
+                            // [ready_for_next_byte] will transition HIGH to request that
+                            // the next byte to be written should be presentaed on [din].
+        .din(din), // Data input for WRITE operation.
+        .ready_for_next_byte(ready_for_next_byte), // A new byte should be presented on [din].
+        .reset(rst), // Resets controller on assertion.
+        .ready(ready), // HIGH if the SD card is ready for a read or write operation.
+        .address(adr), // Memory address for read/write operation. This MUST 
+                            // be a multiple of 512 bytes, due to SD sectoring.
+        .clk(clk25), // 25 MHz clock.
+        .status(state), // For debug purposes: Current state of controller.
+    );
+
+    //
+    //////////////////////////////////////////////////////////////////////////////////
+
+
     CL_fsm fsm (
         .clk(clk),
         .pause_SW(pause_SW),
         .reset_trigger(reset_button),
+
         .pause(pause),
         .reset(reset)
     );
@@ -20,6 +106,7 @@ module CL_block(
         .clk(clk),
         .pause(pause),
         .reset(reset),
+
         .song_time(song_time)
     );
 

Nexys4Game/src/hdl/CL_metadata_controller.v

@@ -0,0 +1,19 @@
+module CL_metadata_controller(
+    input clk, //100mhz clk
+
+
+    output reg loaded
+
+    );
+
+    initial loaded = 0;
+
+
+    //2^12 = 4096 words 
+    mybram #(.LOGSIZE(12),.WIDTH(32)) //WORD:= 3 system bits (0b000 for note, 0b111 for end of data), 6'b for pitch, 3'b for string, 4'b for fret, 16'b for time
+    memory(.addr(),.clk(clk),.we(),.din(),.dout());
+
+
+
+
+endmodule

Nexys4Game/src/hdl/SC_block.v

@@ -41,8 +41,8 @@ module SC_block(
 
     SC_score score (
         .clk(clk),
-        .dt(match_dt),
         .en(match_en),
+        .dt(match_dt),
 
         .score(score)
     );

Nexys4Game/src/hdl/SC_score.v

@@ -1,7 +1,7 @@
 module SC_score(
     input clk, //100mhz clk
-    input [15:0] dt, //margin of correctness for a matched note
     input en, //match enable
+    input [15:0] dt, //margin of correctness for a matched note
 
     output reg [31:0] score //total score ARBITRARY 32 bit width
     );

Nexys4Game/src/hdl/audio_PWM.v

@@ -0,0 +1,27 @@
+`timescale 1ns / 1ps
+// Audio PWM module.
+
+module audio_PWM(
+    input clk, 			// 100MHz clock.
+    input reset,		// Reset assertion.
+    input [7:0] music_data,	// 8-bit music sample
+    output reg PWM_out		// PWM output. Connect this to ampPWM.
+    );
+
+
+    reg [7:0] pwm_counter = 8'd0;           // counts up to 255 clock cycles per pwm period
+
+
+    always @(posedge clk) begin
+        if(reset) begin
+            pwm_counter <= 0;
+            PWM_out <= 0;
+        end
+        else begin
+            pwm_counter <= pwm_counter + 1;
+
+            if(pwm_counter >= music_data) PWM_out <= 0;
+            else PWM_out <= 1;
+        end
+    end
+endmodule

Nexys4Game/src/hdl/clock_4divider.v

@@ -0,0 +1,20 @@
+module clock_4divider(
+    input clk,
+    output reg clk_div
+    );
+    reg counter;
+    initial counter = 0;
+    initial clk_div = 0;
+
+
+    always @(posedge clk) begin
+        if(counter) begin
+            counter <= 0;
+            clk_div <= ~clk_div;
+        end
+        else
+            counter <= 1;
+    end
+
+
+endmodule

Nexys4Game/src/hdl/clock_4divider_tb.v

@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+
+module clock_4divider_tb;
+
+    // Inputs
+    reg clk;
+
+    // Outputs
+    wire clk_div;
+
+    // Instantiate the Unit Under Test (UUT)
+    clock_4divider uut (
+        .clk(clk),
+        .clk_div(clk_div)
+    );
+
+    always #5 clk = !clk;
+    initial begin
+        // Initialize Inputs
+        clk = 0;
+        // Wait 100 ns for global reset to finish
+        #100;
+
+    end
+endmodule

Nexys4Game/src/hdl/labkit_sd.v

@@ -0,0 +1,125 @@
+/* Labkit project demonstrating SD controller use. */
+
+`timescale 1ns / 1ps
+
+// Be sure to enable SD_CD, SD_RESET, SD_SCK, SD_CMD, and SD_DAT in the
+// constraints file.
+module labkit(input CLK100MHZ, input SD_CD, output SD_RESET, output SD_SCK, output SD_CMD, 
+	inout [3:0] SD_DAT, output [15:0] LED, input BTNC);
+
+    // Clock the SD card at 25 MHz.
+	wire clk_100mhz = CLK100MHZ;
+    wire clk_50mhz;
+    wire clk_25mhz;
+    clock_divider div1(clk_100mhz, clk_50mhz);
+    clock_divider div2(clk_50mhz, clk_25mhz);
+
+    wire rst = BTNC;
+    wire spiClk;
+    wire spiMiso;
+    wire spiMosi;
+    wire spiCS;
+
+    // MicroSD SPI/SD Mode/Nexys 4
+    // 1: Unused / DAT2 / SD_DAT[2]
+    // 2: CS / DAT3 / SD_DAT[3]
+    // 3: MOSI / CMD / SD_CMD
+    // 4: VDD / VDD / ~SD_RESET
+    // 5: SCLK / SCLK / SD_SCK
+    // 6: GND / GND / - 
+    // 7: MISO / DAT0 / SD_DAT[0]
+    // 8: UNUSED / DAT1 / SD_DAT[1]
+    assign SD_DAT[2] = 1;
+    assign SD_DAT[3] = spiCS;
+    assign SD_CMD = spiMosi;
+    assign SD_RESET = 0;
+    assign SD_SCK = spiClk;
+    assign spiMiso = SD_DAT[0];
+    assign SD_DAT[1] = 1;
+
+    reg rd = 0;
+    reg wr = 0;
+    reg [7:0] din = 0;
+    wire [7:0] dout;
+    wire byte_available;
+    wire ready;
+    wire ready_for_next_byte;
+    reg [31:0] adr = 32'h00_00_00_00;
+
+    reg [15:0] bytes = 0;
+    reg [1:0] bytes_read = 0;
+
+    wire [4:0] state;
+
+    parameter STATE_INIT = 0;
+    parameter STATE_START = 1;
+    parameter STATE_WRITE = 2;
+    parameter STATE_READ = 3;
+    reg [1:0] test_state = STATE_INIT; 
+    assign LED = {state, ready, test_state, bytes[15:8]};
+
+    sd_controller sdcont(.cs(spiCS), .mosi(spiMosi), .miso(spiMiso),
+            .sclk(spiClk), .rd(rd), .wr(wr), .reset(rst),
+            .din(din), .dout(dout), .byte_available(byte_available),
+            .ready(ready), .address(adr), 
+            .ready_for_next_byte(ready_for_next_byte), .clk(clk_25mhz), 
+            .status(state));
+
+
+    always @(posedge clk_25mhz) begin
+        if(rst) begin
+            bytes <= 0;
+            bytes_read <= 0;
+            din <= 0;
+            wr <= 0;
+            rd <= 0;
+            test_state <= STATE_INIT; 
+        end
+        else begin
+            case (test_state)
+                STATE_INIT: begin
+                    if(ready) begin
+                        test_state <= STATE_START;
+                        wr <= 1;
+                        din <= 8'hAA;
+                    end
+                end
+                STATE_START: begin
+                    if(ready == 0) begin
+                        test_state <= STATE_WRITE;
+                        wr <= 0;
+                    end
+                end
+                STATE_WRITE: begin
+                    if(ready) begin
+                        test_state <= STATE_READ;
+                        rd <= 1;
+                    end
+                    else if(ready_for_next_byte) begin
+                        din <= 8'hAA;
+                    end
+                end
+                STATE_READ: begin
+                    if(byte_available) begin
+                        rd <= 0;
+                        if(bytes_read == 0) begin
+                            bytes_read <= 1;
+                            bytes[15:8] <= dout;
+                        end
+                        else if(bytes_read == 1) begin
+                            bytes_read <= 2;
+                            bytes[7:0] <= dout;
+
+                        end
+                    end
+                end
+            endcase
+        end
+    end
+endmodule
+
+module clock_divider(input clk_in, output reg clk_out = 0);
+	always @(posedge clk_in) begin
+		clk_out <= ~clk_out;
+	end
+endmodule

Nexys4Game/src/hdl/mybram.v

@@ -0,0 +1,22 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Verilog equivalent to a BRAM, tools will infer the right thing!
+// number of locations = 1<<LOGSIZE, width in bits = WIDTH.
+// default is a 16K x 1 memory.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+module mybram #(parameter LOGSIZE=14, WIDTH=1)
+              (input wire [LOGSIZE-1:0] addr,
+               input wire clk,
+               input wire [WIDTH-1:0] din,
+               output reg [WIDTH-1:0] dout,
+               input wire we);
+   // let the tools infer the right number of BRAMs
+   (* ram_style = "block" *)
+   reg [WIDTH-1:0] mem[(1<<LOGSIZE)-1:0];
+   always @(posedge clk) begin
+     if (we) mem[addr] <= din;
+     dout <= mem[addr];
+   end
+endmodule