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move the conditional part of
toolchain.build(run=True/False)
to a separate method
#258
opened Feb 22, 2022 by
lneuhaus
Migen - Cat() simulation not matching verilog when Cat_object is sliced
#228
opened Dec 6, 2020 by
scted
[migen][sim] How to import verilog source into migen design file ?
question
#188
opened Jul 8, 2019 by
henrydang80
.part() is converted to Verilog that can evaluate to 'x
bug
fixed-in-nmigen
#168
opened Dec 16, 2018 by
whitequark
Finalization is order-dependent, leading to footguns
bug
fixed-in-nmigen
#158
opened Nov 10, 2018 by
whitequark
Negative initialization produces incorrect verilog
bug
fixed-in-nmigen
#142
opened Oct 9, 2018 by
JohnSully
Python logical operator 'and' silently dropped
bug
fixed-in-nmigen
#137
opened Sep 27, 2018 by
tdaede
Migen outputs incorrect verilog in specific use-case
bug
fixed-in-nmigen
#119
opened Jul 4, 2018 by
rohitk-singh
review expression size and signedness
fixed-in-nmigen
improvement
#115
opened Jun 10, 2018 by
jordens
Empty FSM states do not produce expected behavior
bug
fixed-in-nmigen
#112
opened May 28, 2018 by
whitequark
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