Start the restructure

leros-dev · Jul 25, 2024 · 13fe674 · 13fe674
1 parent 82448fe
commit 13fe674
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Showing 3 changed files with 19 additions and 11 deletions.
diff --git a/src/main/scala/leros/Decode.scala b/src/main/scala/leros/Decode.scala
@@ -23,7 +23,6 @@ class DecodeOut extends Bundle {
   val isLoadIndB = Bool()
   val isLoadIndH = Bool()
   val isDataAccess = Bool()
-  val isLoadAddr = Bool()
   val isBranch = Bool()
   val brType = UInt(4.W)
   val exit = Bool()
@@ -52,7 +51,6 @@ object DecodeOut {
     v.isLoadIndB := false.B
     v.isLoadIndH := false.B
     v.isDataAccess := false.B
-    v.isLoadAddr := false.B
     v.isBranch := false.B
     v.brType := 0.U
     v.exit := false.B
@@ -189,7 +187,7 @@ class Decode() extends Module {
       d.isStore := true.B
     }
     is (LDADDR.U) {
-      d.isLoadAddr := true.B
+      d.nextState := loadAddr
     }
     is (LDIND.U) {
       d.isDataAccess := true.B

diff --git a/src/main/scala/leros/Leros.scala b/src/main/scala/leros/Leros.scala
@@ -76,20 +76,26 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends LerosBa
 
   val stateReg = RegInit(fetch)
 
+  when (stateReg =/= fetch) {
+    stateReg := fetch
+    pcReg := pcNext
+    alu.io.enaMask := decReg.enaMask
+  }
+
   switch(stateReg) {
     is (fetch) {
       stateReg := decout.nextState
       decReg := decout
     }
 
+    // where is the "normal" ALU operation?
+
+    is (loadAddr) {
+      addrReg := dataRead
+      alu.io.enaMask := 0.U
+    }
     is (execute) {
-      stateReg := fetch
-      pcReg := pcNext
-      alu.io.enaMask := decReg.enaMask
-      when(decReg.isLoadAddr) {
-        addrReg := dataRead
-        alu.io.enaMask := 0.U
-      }
+
       when(decReg.isLoadInd) {
         // nothing to be done here
       }
@@ -110,6 +116,7 @@ class Leros(prog: String, size: Int = 32, memAddrWidth: Int = 8) extends LerosBa
         outReg := accu
       }
       when(decReg.isStoreIndB) {
+        // wr and wrMask could be set in decode and registered
         dataMem.io.wr := true.B
         dataMem.io.wrMask := "b0001".U << effAddrOffReg
         alu.io.enaMask := 0.U

diff --git a/src/main/scala/leros/State.scala b/src/main/scala/leros/State.scala
@@ -2,5 +2,8 @@ package leros
 
 import chisel3.ChiselEnum
 object State extends ChiselEnum {
-  val fetch, execute = Value
+  val fetch, execute,
+  loadAddr, loadInd, loadIndB, loadIndH,
+  store, storeInd, storeindB, storeIndH,
+  branch, jal = Value
 }