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fixes hdl-util#43: enforce hdmi 12px minimum control period during vi…
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…deo and data-island preambles; fixed off-by-one errors on VG, VP, and VSync; fixed test bench
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krisd committed Aug 20, 2023
1 parent b5bc3d7 commit bebe1aa
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Showing 2 changed files with 15 additions and 12 deletions.
21 changes: 12 additions & 9 deletions src/hdmi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -192,9 +192,9 @@ always_comb begin
hsync <= invert ^ (cx >= screen_width + hsync_pulse_start && cx < screen_width + hsync_pulse_start + hsync_pulse_size);
// vsync pulses should begin and end at the start of hsync, so special
// handling is required for the lines on which vsync starts and ends
if (cy == screen_height + vsync_pulse_start)
if (cy == screen_height + vsync_pulse_start - 1)
vsync <= invert ^ (cx >= screen_width + hsync_pulse_start);
else if (cy == screen_height + vsync_pulse_start + vsync_pulse_size)
else if (cy == screen_height + vsync_pulse_start + vsync_pulse_size - 1)
vsync <= invert ^ (cx < screen_width + hsync_pulse_start);
else
vsync <= invert ^ (cy >= screen_height + vsync_pulse_start && cy < screen_height + vsync_pulse_start + vsync_pulse_size);
Expand Down Expand Up @@ -254,8 +254,8 @@ generate
end
else
begin
video_guard <= cx >= frame_width - 2 && cx < frame_width && (cy == frame_height - 1 || cy < screen_height);
video_preamble <= cx >= frame_width - 10 && cx < frame_width - 2 && (cy == frame_height - 1 || cy < screen_height);
video_guard <= cx >= frame_width - 2 && cx < frame_width && (cy == frame_height - 1 || cy < screen_height - 1 /* no VG at end of last line */);
video_preamble <= cx >= frame_width - 10 && cx < frame_width - 2 && (cy == frame_height - 1 || cy < screen_height - 1 /* no VP at end of last line */);
end
end

Expand All @@ -264,17 +264,17 @@ generate
logic [4:0] num_packets_alongside;
always_comb
begin
max_num_packets_alongside = ((frame_width - screen_width) /* VD period */ - 2 /* V guard */ - 8 /* V preamble */ - 12 /* 12px control period */ - 2 /* DI guard */ - 2 /* DI start guard */ - 8 /* DI premable */) / 32;
max_num_packets_alongside = (frame_width - screen_width /* VD period */ - 2 /* V guard */ - 8 /* V preamble */ - 4 /* Min V control period */ - 2 /* DI trailing guard */ - 2 /* DI leading guard */ - 8 /* DI premable */ - 4 /* Min DI control period */) / 32;
if (max_num_packets_alongside > 18)
num_packets_alongside = 5'd18;
else
num_packets_alongside = 5'(max_num_packets_alongside);
end

logic data_island_period_instantaneous;
assign data_island_period_instantaneous = num_packets_alongside > 0 && cx >= screen_width + 10 && cx < screen_width + 10 + num_packets_alongside * 32;
assign data_island_period_instantaneous = num_packets_alongside > 0 && cx >= screen_width + 14 && cx < screen_width + 14 + num_packets_alongside * 32;
logic packet_enable;
assign packet_enable = data_island_period_instantaneous && 5'(cx + screen_width + 22) == 5'd0;
assign packet_enable = data_island_period_instantaneous && 5'(cx + screen_width + 18) == 5'd0;

logic data_island_guard = 0;
logic data_island_preamble = 0;
Expand All @@ -289,8 +289,11 @@ generate
end
else
begin
data_island_guard <= num_packets_alongside > 0 && ((cx >= screen_width + 8 && cx < screen_width + 10) || (cx >= screen_width + 10 + num_packets_alongside * 32 && cx < screen_width + 10 + num_packets_alongside * 32 + 2));
data_island_preamble <= num_packets_alongside > 0 && cx >= screen_width && cx < screen_width + 8;
data_island_guard <= num_packets_alongside > 0 && (
(cx >= screen_width + 12 && cx < screen_width + 14) /* leading guard */ ||
(cx >= screen_width + 14 + num_packets_alongside * 32 && cx < screen_width + 14 + num_packets_alongside * 32 + 2) /* trailing guard */
);
data_island_preamble <= num_packets_alongside > 0 && cx >= screen_width + 4 && cx < screen_width + 12;
data_island_period <= data_island_period_instantaneous;
end
end
Expand Down
6 changes: 3 additions & 3 deletions test/top_tb/top_tb.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -110,13 +110,13 @@ always @(posedge top.clk_pixel)
begin
cx <= cx == top.frame_width - 1 ? 0 : cx + 1;
cy <= cx == top.frame_width-1'b1 ? cy == top.frame_height-1'b1 ? 0 : cy + 1'b1 : cy;
if (top.hdmi.true_hdmi_output.num_packets_alongside > 0 && (cx >= top.screen_width + 8 && cx < top.screen_width + 10) || (cx >= top.screen_width + 10 + top.hdmi.true_hdmi_output.num_packets_alongside * 32 && cx < top.screen_width + 10 + top.hdmi.true_hdmi_output.num_packets_alongside * 32 + 2))
if (top.hdmi.true_hdmi_output.num_packets_alongside > 0 && (cx >= top.screen_width + 12 && cx < top.screen_width + 14) || (cx >= top.screen_width + 14 + top.hdmi.true_hdmi_output.num_packets_alongside * 32 && cx < top.screen_width + 14 + top.hdmi.true_hdmi_output.num_packets_alongside * 32 + 2))
begin
assert(tmds_values[2] == 10'b0100110011) else $fatal("Channel 2 DI GB incorrect: %b", tmds_values[2]);
assert(tmds_values[1] == 10'b0100110011) else $fatal("Channel 1 DI GB incorrect");
assert(tmds_values[0] == 10'b1010001110 || tmds_values[0] == 10'b1001110001 || tmds_values[0] == 10'b0101100011 || tmds_values[0] == 10'b1011000011) else $fatal("Channel 0 DI GB incorrect");
end
else if (top.hdmi.true_hdmi_output.num_packets_alongside > 0 && cx >= top.screen_width + 10 && cx < top.screen_width + 10 + top.hdmi.true_hdmi_output.num_packets_alongside * 32)
else if (top.hdmi.true_hdmi_output.num_packets_alongside > 0 && cx >= top.screen_width + 14 && cx < top.screen_width + 14 + top.hdmi.true_hdmi_output.num_packets_alongside * 32)
begin
data_counter <= data_counter + 1'd1;
if (data_counter == 0)
Expand All @@ -126,7 +126,7 @@ begin
sub[1][63:1] <= 63'dX;
sub[0][63:1] <= 63'dX;
header[31:1] <= 31'dX;
if (cx != top.screen_width + 10 || !first_packet) // Packet complete
if (cx != top.screen_width + 14 || !first_packet) // Packet complete
begin
first_packet <= 0;
case(header[7:0])
Expand Down

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