[SX127x] Fix FSK address handling

jgromes · Oct 12, 2024 · 1650480 · 1650480
1 parent e9b6e27
commit 1650480
Showing 1 changed file with 10 additions and 8 deletions.
diff --git a/src/modules/SX127x/SX127x.cpp b/src/modules/SX127x/SX127x.cpp
@@ -605,16 +605,18 @@ int16_t SX127x::startTransmit(const uint8_t* data, size_t len, uint8_t addr) {
       this->mod->SPIsetRegValue(RADIOLIB_SX127X_REG_DIO_MAPPING_1, RADIOLIB_SX127X_DIO0_PACK_PACKET_SENT, 7, 6);
     }
 
-    // set packet length
-    if (this->packetLengthConfig == RADIOLIB_SX127X_PACKET_VARIABLE) {
-      this->mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, len);
-    }
-
-    // check address filtering
+    // set packet length - increased by 1 when address filter is enabled
     uint8_t filter = this->mod->SPIgetRegValue(RADIOLIB_SX127X_REG_PACKET_CONFIG_1, 2, 1);
-    if((filter == RADIOLIB_SX127X_ADDRESS_FILTERING_NODE) || (filter == RADIOLIB_SX127X_ADDRESS_FILTERING_NODE_BROADCAST)) {
-      this->mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, addr);
+    if(this->packetLengthConfig == RADIOLIB_SX127X_PACKET_VARIABLE) {
+      if((filter == RADIOLIB_SX127X_ADDRESS_FILTERING_NODE) || (filter == RADIOLIB_SX127X_ADDRESS_FILTERING_NODE_BROADCAST)) {
+        this->mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, len + 1);
+        this->mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, addr);
+      } else {
+        this->mod->SPIwriteRegister(RADIOLIB_SX127X_REG_FIFO, len);
+      }
+
     }
+
   }
 
   // write packet to FIFO