Merge OpenAI Triton commit 3613bf4
#2574
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Note, there are no uses of `nvgpu::` in this lib. Unblocks building `*-opt` tools with "custom" LLVM that was built with `-DLLVM_TARGETS_TO_BUILD="host;AMDGPU"` (i.e., no `NVPTX`).
This PR implements general conversion of MFMA dot operand to Linear Layout.
Hopper supports vectorized atomics for add, max, and min. This PR adds support for generating these instructions. Note: atomic add/min/max also have packed instructions for f16x2 and bf16x2. Packed instructions were used prior to this PR, but vectorized instructions weren't. When vectorized instructions are available, this PR switches to using vectorized instructions (like .v2.f16 instead of .f16x2, or .v8.f16 instead of .v4.f16x2). When vectorized instructions aren't available, packed instructions will be used instead. This PR also adds a check for mask alignment, which wasn't previously checked.
…4974) This is a quick follow-up for the recent autotuner/testing changes as in triton-lang/triton#4496. This PR moves the empty cache creation into the driver code to make the code more device independent.
…d (#4980) The bitwidth is unimplemented in LLVM for pointer types so it throws an exception when evaluating the condition `tensorTy.getElementType().getIntOrFloatBitWidth()`
This commit refactors the AccelerateAMDMatmul patterns in prep for mxfp support.
pbchekin
approved these changes
Oct 25, 2024
whitneywhtsang
changed the title
3c13f093613bf4
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This PR change the Triton base from 1064b59 to 3613bf4 (Oct 24).
Pass rate: 98.98%
Please do not squash and merge this PR.