Fix module names in export of verilog testbenches

[olofos]

When exporting verilog testbenches, module names are not properly escaped.

For example, if the file "My-file" contains a test named "My-test" then the module declaration for the testbench will start with module My-file_My-test_tb; and the instantiation of the "My-file" module will look like \My-file \My-file 0 (...). In both cases the hyphen makes the names illegal verilog identifiers.

With this PR you will instead get module \My-file_My-test_tb ; and \My-file \My-file0 (...)

I've added a new test file in "src/test/resources/dig/hdl_names/a-b.dig" and two tests that use this file. I'm not sure if this is the nicest way of writing these tests