Merge pull request #322 from abrisco/exectools

Add `data` attribute to `verilog_library`

synthesis/build_defs.bzl

@@ -64,7 +64,8 @@ def _create_flist(ctx, flist_tag, files, short_path = False):
 def _synthesize_design_impl(ctx):
     transitive_srcs = _transitive_srcs([dep for dep in ctx.attr.deps if VerilogInfo in dep])
     verilog_srcs = [verilog_info_struct.srcs for verilog_info_struct in transitive_srcs.to_list()]
-    verilog_files = [src for sub_tuple in verilog_srcs for src in sub_tuple]
+    verilog_data = [verilog_info_struct.data for verilog_info_struct in transitive_srcs.to_list()]
+    verilog_files = [src for sub_tuple in (verilog_srcs + verilog_data) for src in sub_tuple]
     verilog_hdrs = [verilog_info_struct.hdrs for verilog_info_struct in transitive_srcs.to_list()]
     verilog_hdr_files = [hdr for sub_tuple in verilog_hdrs for hdr in sub_tuple]
 

verilator/defs.bzl

@@ -74,7 +74,10 @@ def cc_compile_and_link_static_library(ctx, srcs, hdrs, deps, runfiles, includes
         output_files.append(linking_output.library_to_link.dynamic_library)
 
     return [
-        DefaultInfo(files = depset(output_files), runfiles = ctx.runfiles(files = runfiles)),
+        DefaultInfo(
+            files = depset(output_files),
+            runfiles = ctx.runfiles(files = runfiles),
+        ),
         CcInfo(
             compilation_context = compilation_context,
             linking_context = linking_context,
@@ -100,7 +103,8 @@ def _only_hpp(f):
 def _verilator_cc_library(ctx):
     transitive_srcs = depset([], transitive = [ctx.attr.module[VerilogInfo].dag])
     all_srcs = [verilog_info_struct.srcs for verilog_info_struct in transitive_srcs.to_list()]
-    all_files = [src for sub_tuple in all_srcs for src in sub_tuple]
+    all_data = [verilog_info_struct.data for verilog_info_struct in transitive_srcs.to_list()]
+    all_files = [src for sub_tuple in (all_srcs + all_data) for src in sub_tuple]
 
     # Filter out .dat files.
     runfiles = []

verilator/tests/BUILD

@@ -47,6 +47,8 @@ verilog_library(
     name = "load_and_count",
     srcs = [
         "load_and_count.sv",
+    ],
+    data = [
         "test_data.dat",
     ],
 )

verilog/providers.bzl

@@ -24,7 +24,7 @@ VerilogInfo = provider(
     },
 )
 
-def make_dag_entry(srcs, hdrs, deps, label):
+def make_dag_entry(srcs, hdrs, data, deps, label):
     """Create a new DAG entry for use in VerilogInfo.
 
     As VerilogInfo should be created via 'merge_verilog_info' (rather than directly),
@@ -39,6 +39,7 @@ def make_dag_entry(srcs, hdrs, deps, label):
     Args:
       srcs: A list of File that are 'srcs'.
       hdrs: A list of File that are 'hdrs'.
+      data: A list of File that are `data`.
       deps: A list of Label that are deps of this entry.
       label: A Label to use as the name for this entry.
     Returns:
@@ -47,6 +48,7 @@ def make_dag_entry(srcs, hdrs, deps, label):
     return struct(
         srcs = tuple(srcs),
         hdrs = tuple(hdrs),
+        data = tuple(data),
         deps = tuple(deps),
         label = label,
     )
@@ -69,7 +71,7 @@ def make_verilog_info(
       # dpis: Verilog DPI files.
     Returns:
       VerilogInfo that combines all the DAGs together.
-      """
+    """
     return VerilogInfo(
         dag = depset(
             direct = new_entries,
@@ -91,6 +93,7 @@ def _verilog_library_impl(ctx):
     verilog_info = make_verilog_info(
         new_entries = [make_dag_entry(
             srcs = ctx.files.srcs,
+            data = ctx.files.data,
             hdrs = ctx.files.hdrs,
             deps = ctx.attr.deps,
             label = ctx.label,
@@ -106,6 +109,10 @@ verilog_library = rule(
     doc = "Define a Verilog module.",
     implementation = _verilog_library_impl,
     attrs = {
+        "data": attr.label_list(
+            doc = "Compile data ready by sources.",
+            allow_files = True,
+        ),
         "deps": attr.label_list(
             doc = "The list of other libraries to be linked.",
             providers = [
@@ -114,11 +121,11 @@ verilog_library = rule(
         ),
         "hdrs": attr.label_list(
             doc = "Verilog or SystemVerilog headers.",
-            allow_files = True,
+            allow_files = [".vh", ".svh"],
         ),
         "srcs": attr.label_list(
             doc = "Verilog or SystemVerilog sources.",
-            allow_files = True,
+            allow_files = [".v", ".sv"],
         ),
     },
 )

vivado/README.md

@@ -1,5 +1,7 @@
 # Vivado rules
 
+Bazel rules for the [Vivado Design Suite](https://www.xilinx.com/developer/products/vivado.html).
+
 The following are defined in `//vivado:defs.bzl`:
 
 * `vivado_create_project`

vivado/defs.bzl

@@ -98,7 +98,8 @@ def generate_file_load_tcl(module):
     """
     transitive_srcs = depset([], transitive = [module[VerilogInfo].dag])
     all_srcs = [verilog_info_struct.srcs for verilog_info_struct in transitive_srcs.to_list()]
-    all_files = [src for sub_tuple in all_srcs for src in sub_tuple]
+    all_data = [verilog_info_struct.data for verilog_info_struct in transitive_srcs.to_list()]
+    all_files = [src for sub_tuple in (all_srcs + all_data) for src in sub_tuple]
 
     hdl_source_content, constraints_content, tcl_content = get_content_from_files(all_files)
 

vivado/tests/BUILD

@@ -12,8 +12,8 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+load("@bazel_skylib//rules:write_file.bzl", "write_file")
 load("@rules_cc//cc:defs.bzl", "cc_test")
-load("@rules_python//python:defs.bzl", "py_binary")
 load("//verilator:defs.bzl", "verilator_cc_library")
 load("//verilog:defs.bzl", "verilog_library")
 load(
@@ -33,6 +33,8 @@ verilog_library(
     name = "johnson_counter",
     srcs = [
         "johnson_counter.sv",
+    ],
+    data = [
         "test.mem",
     ],
 )
@@ -70,8 +72,10 @@ xsim_test(
 verilog_library(
     name = "johnson_counter_top",
     srcs = [
-        "io_constraints.xdc",
         "johnson_counter_top.sv",
+    ],
+    data = [
+        "io_constraints.xdc",
         "zcu111_gpio.tcl",
     ],
     deps = [
@@ -88,24 +92,31 @@ vivado_flow(
     xilinx_env = ":xilinx_env.sh",
 )
 
-py_binary(
-    name = "gen_values",
-    srcs = ["gen_values.py"],
-)
-
-genrule(
+write_file(
     name = "test_mem",
-    outs = ["test.mem"],
-    cmd = "$(location :gen_values) > $(OUTS)",
-    tools = [":gen_values"],
+    out = "test.mem",
+    content = [
+        "00",
+        "05",
+        "0A",
+        "0F",
+        "14",
+        "19",
+        "1E",
+        "28",
+        "",
+    ],
+    newline = "unix",
 )
 
 verilog_library(
     name = "weights_replay",
     srcs = [
-        "test.mem",
         "weights_replay.sv",
     ],
+    data = [
+        "test.mem",
+    ],
 )
 
 verilator_cc_library(
@@ -131,6 +142,8 @@ verilog_library(
     name = "weights_replay_top",
     srcs = [
         "weights_replay_top.sv",
+    ],
+    data = [
         "zcu111_weights.tcl",
     ],
 )
@@ -194,7 +207,7 @@ vivado_create_ip(
 
 verilog_library(
     name = "weights_replay_and_save_bd",
-    srcs = [
+    data = [
         "weights_replay_and_save_bd.tcl",
     ],
 )