Add a note about data cache.

src/tusb_option.h

@@ -243,6 +243,10 @@
 //--------------------------------------------------------------------+
 
 // DWC2 controller: use DMA for data transfer
+// For processors with data cache enabled, USB endpoint buffer region
+// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
+// For example, on Cortex-M7 the MPU region can be configured as normal
+// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
 #ifndef CFG_TUD_DWC2_DMA
   #define CFG_TUD_DWC2_DMA 0
 #endif