v4.12.0 (#4)

Co-authored-by: HailoRT-Automation <[email protected]>

README.md

@@ -9,14 +9,18 @@ Hailo's PCIe driver is required when working with a Hailo device via the PCIe in
 and the device, and loads the device's firmware when working through this interface. The device driver
 is used to manage the Hailo device, communicate with the device and transfer data to/from the device.
 
-## Usage
+## Usage and Compilation
 
 See [**hailo.ai developer zone documentation**](https://hailo.ai/developer-zone/documentation/hailort/latest/?sp_referrer=drivers/pcie_linux.html) (registration is required for  full documentation access).
 
 ## Changelog
 
 See [**hailo.ai developer zone - HailoRT changelog**](https://hailo.ai/developer-zone/documentation/hailort/latest/?sp_referrer=changelog/changelog.html) (registration required).
 
+## License
+
+Distributed under the [**GNU General Public License version 2 license**](https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html)
+
 ## Contact
 
 Contact information and support is available at [**hailo.ai**](https://hailo.ai/contact-us/).

common/common_fw_logger.c → common/fw_operation.c

@@ -1,20 +1,34 @@
 // SPDX-License-Identifier: GPL-2.0
 /**
- * Copyright (c) 2019-2022 Hailo Technologies Ltd. All rights reserved.
- **/
+ * Copyright (c) 2022 Hailo Technologies Ltd. All rights reserved.
+**/
 
-#include "types.h"
-#include "common_fw_logger.h"
-#include "hailo_resource.h"
+#include "fw_operation.h"
 
-#ifdef __linux__
-#if LINUX_VERSION_CODE >= KERNEL_VERSION( 5, 0, 0 )
-#define compatible_access_ok(a,b,c) access_ok(b, c)
-#else
-#define compatible_access_ok(a,b,c) access_ok(a, b, c)
-#endif
+typedef struct {
+    uint32_t host_offset;
+    uint32_t chip_offset;
+} FW_DEBUG_BUFFER_HEADER_t;
 
-#endif // ifdef __linux__
+#define DEBUG_BUFFER_DATA_SIZE (DEBUG_BUFFER_TOTAL_SIZE - sizeof(FW_DEBUG_BUFFER_HEADER_t))
+
+int hailo_read_firmware_notification(struct hailo_resource *resource, struct hailo_d2h_notification *notification)
+{
+    hailo_d2h_buffer_details_t d2h_buffer_details = {0, 0};
+    hailo_resource_read_buffer(resource, 0, sizeof(d2h_buffer_details),
+        &d2h_buffer_details);
+
+    if ((sizeof(notification->buffer) < d2h_buffer_details.buffer_len) || (0 == d2h_buffer_details.is_buffer_in_use)) {
+        return -EINVAL;
+    }
+
+    notification->buffer_len = d2h_buffer_details.buffer_len;
+    hailo_resource_read_buffer(resource, sizeof(d2h_buffer_details), notification->buffer_len, notification->buffer);
+
+    // Write is_buffer_in_use = false
+    hailo_resource_write16(resource, 0, 0);
+    return 0;
+}
 
 static inline size_t calculate_log_ready_to_read(FW_DEBUG_BUFFER_HEADER_t *header)
 {

common/fw_operation.h

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * Copyright (c) 2022 Hailo Technologies Ltd. All rights reserved.
+**/
+
+#ifndef _HAILO_COMMON_FIRMWARE_OPERATION_H_
+#define _HAILO_COMMON_FIRMWARE_OPERATION_H_
+
+#include "types.h"
+#include "hailo_resource.h"
+
+#ifdef __linux__
+#include "utils/compact.h"
+#endif // ifdef __linux__
+
+#define DEBUG_BUFFER_TOTAL_SIZE (4*1024)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int hailo_read_firmware_notification(struct hailo_resource *resource, struct hailo_d2h_notification *notification);
+
+long hailo_read_firmware_log(struct hailo_resource *fw_logger_resource, struct hailo_read_log_params *params);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAILO_COMMON_FIRMWARE_OPERATION_H_ */

common/common_fw_validation.c → common/fw_validation.c

@@ -5,7 +5,7 @@
 
 #include "types.h"
 
-#include "common_fw_validation.h"
+#include "fw_validation.h"
 
 
 
@@ -33,10 +33,10 @@ int FW_VALIDATION__validate_fw_header(uintptr_t firmware_base_address,
     CONSUME_FIRMWARE(sizeof(firmware_header_t), -EINVAL);
 
     switch (board_type) {
-    case HAILO8:
+    case HAILO_BOARD_TYPE_HAILO8:
         expected_firmware_magic = FIRMWARE_HEADER_MAGIC_HAILO8; 
         break;
-    case HAILO_MERCURY:
+    case HAILO_BOARD_TYPE_MERCURY:
         expected_firmware_magic = FIRMWARE_HEADER_MAGIC_MERCURY; 
         break;
     default:

common/hailo_ioctl_common.h

@@ -6,6 +6,9 @@
 #ifndef _HAILO_IOCTL_COMMON_H_
 #define _HAILO_IOCTL_COMMON_H_
 
+
+#define DESCRIPTORS_IN_BUFFER(buffer_size, desc_page_size) (((buffer_size) + (desc_page_size) - 1) / (desc_page_size))
+
 // This value is not easily changeable.
 // For example: the channel interrupts ioctls assume we have up to 32 channels
 #define MAX_VDMA_CHANNELS_PER_ENGINE    (32)
@@ -84,6 +87,11 @@ struct hailo_channel_interrupt_timestamp {
     uint16_t desc_num_processed;
 };
 
+typedef struct {
+    uint16_t is_buffer_in_use;
+    uint16_t buffer_len;
+} hailo_d2h_buffer_details_t;
+
 // This struct is the same as `enum dma_data_direction` (defined in linux/dma-direction)
 enum hailo_dma_data_direction {
     HAILO_DMA_BIDIRECTIONAL = 0,
@@ -145,16 +153,14 @@ struct hailo_desc_list_bind_vdma_buffer_params {
     uintptr_t desc_handle;      // in
     uint16_t desc_page_size;    // in
     uint8_t channel_index;      // in
+    size_t offset;              // in
 };
 
 /* structure used in ioctl HAILO_VDMA_CHANNEL_ENABLE */
 struct hailo_vdma_channel_enable_params {
     uint8_t engine_index;                       // in
     uint8_t channel_index;                      // in
     enum hailo_dma_data_direction direction;    // in
-    // If desc_list_handle is set to valid handle (different than INVALID_DRIVER_HANDLE_VALUE),
-    // the driver will start the channel with the given descriptors list.
-    uintptr_t desc_list_handle;                 // in
     bool enable_timestamps_measure;             // in
     uint64_t channel_handle;                    // out
 };
@@ -221,9 +227,9 @@ struct hailo_fw_control {
     enum hailo_cpu_id cpu_id;
 };
 
-/* structure used in ioctl HAILO_BAR_TRANSFER */
+/* structure used in ioctl HAILO_MEMORY_TRANSFER */
 // Max bar transfer size gotten from ATR0_TABLE_SIZE
-#define MAX_BAR_TRANSFER_LENGTH  (4096)
+#define MAX_MEMORY_TRANSFER_LENGTH  (4096)
 
 enum hailo_transfer_direction {
     TRANSFER_READ = 0,
@@ -233,12 +239,34 @@ enum hailo_transfer_direction {
     TRANSFER_MAX_ENUM = INT_MAX,
 };
 
-struct hailo_bar_transfer_params {
+enum hailo_transfer_memory_type {
+    HAILO_TRANSFER_DEVICE_DIRECT_MEMORY,
+
+    // vDMA memories
+    HAILO_TRANSFER_MEMORY_VDMA0 = 0x100,
+    HAILO_TRANSFER_MEMORY_VDMA1,
+    HAILO_TRANSFER_MEMORY_VDMA2,
+
+    // PCIe driver memories
+    HAILO_TRANSFER_MEMORY_PCIE_BAR0 = 0x200,
+    HAILO_TRANSFER_MEMORY_PCIE_BAR2 = 0x202,
+    HAILO_TRANSFER_MEMORY_PCIE_BAR4 = 0x204,
+
+    // DRAM DMA driver memories
+    HAILO_TRANSFER_MEMORY_DMA_ENGINE0 = 0x300,
+    HAILO_TRANSFER_MEMORY_DMA_ENGINE1,
+    HAILO_TRANSFER_MEMORY_DMA_ENGINE2,
+
+    /** Max enum value to maintain ABI Integrity */
+    HAILO_TRANSFER_MEMORY_MAX_ENUM = INT_MAX,
+};
+
+struct hailo_memory_transfer_params {
     enum hailo_transfer_direction transfer_direction;   // in
-    uint32_t bar_index;                                 // in
-    off_t offset;                                       // in
+    enum hailo_transfer_memory_type memory_type;        // in
+    uint64_t address;                                   // in
     size_t count;                                       // in
-    uint8_t buffer[MAX_BAR_TRANSFER_LENGTH];            // in/out
+    uint8_t buffer[MAX_MEMORY_TRANSFER_LENGTH];         // in/out
 };
 
 /* structure used in ioctl HAILO_VDMA_CHANNEL_READ_REGISTER */
@@ -286,10 +314,12 @@ struct hailo_d2h_notification {
 };
 
 enum hailo_board_type {
-    HAILO8 = 0,
-    HAILO_MERCURY,
-    HAILO_BOARD_COUNT,
-    HAILO_INVALID_BOARD = 0xFFFFFFFF,
+    HAILO_BOARD_TYPE_HAILO8 = 0,
+    HAILO_BOARD_TYPE_MERCURY,
+    HAILO_BOARD_TYPE_COUNT,
+
+    /** Max enum value to maintain ABI Integrity */
+    HAILO_BOARD_TYPE_MAX_ENUM = INT_MAX
 };
 
 enum hailo_dma_type {
@@ -306,6 +336,7 @@ struct hailo_device_properties {
     enum hailo_allocation_mode   allocation_mode;
     enum hailo_dma_type          dma_type;
     size_t                       dma_engines_count;
+    bool                         is_fw_loaded;
 #ifdef __QNX__
     pid_t                        resource_manager_pid;
 #endif // __QNX__
@@ -345,7 +376,7 @@ struct hailo_allocate_continuous_buffer_params {
 #pragma pack(pop)
 
 enum hailo_general_ioctl_code {
-    HAILO_BAR_TRANSFER_CODE,
+    HAILO_MEMORY_TRANSFER_CODE,
     HAILO_FW_CONTROL_CODE,
     HAILO_READ_NOTIFICATION_CODE,
     HAILO_DISABLE_NOTIFICATION_CODE,
@@ -358,7 +389,7 @@ enum hailo_general_ioctl_code {
     HAILO_GENERAL_IOCTL_MAX_NR,
 };
 
-#define HAILO_BAR_TRANSFER              _IOWR_(HAILO_GENERAL_IOCTL_MAGIC,  HAILO_BAR_TRANSFER_CODE,               struct hailo_bar_transfer_params)
+#define HAILO_MEMORY_TRANSFER           _IOWR_(HAILO_GENERAL_IOCTL_MAGIC,  HAILO_MEMORY_TRANSFER_CODE,            struct hailo_memory_transfer_params)
 #define HAILO_FW_CONTROL                _IOWR_(HAILO_GENERAL_IOCTL_MAGIC,  HAILO_FW_CONTROL_CODE,                 struct hailo_fw_control)
 #define HAILO_READ_NOTIFICATION         _IOW_(HAILO_GENERAL_IOCTL_MAGIC,   HAILO_READ_NOTIFICATION_CODE,          struct hailo_d2h_notification)
 #define HAILO_DISABLE_NOTIFICATION      _IO_(HAILO_GENERAL_IOCTL_MAGIC,    HAILO_DISABLE_NOTIFICATION_CODE)
@@ -391,13 +422,13 @@ enum hailo_vdma_ioctl_code {
     HAILO_VDMA_IOCTL_MAX_NR,
 };
 
-#define HAILO_VDMA_CHANNEL_ENABLE           _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_ENABLE_CODE,        struct hailo_vdma_channel_enable_params)
-#define HAILO_VDMA_CHANNEL_DISABLE          _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_DISABLE_CODE,       struct hailo_vdma_channel_disable_params)
-#define HAILO_VDMA_CHANNEL_WAIT_INT         _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_WAIT_INT_CODE,      struct hailo_vdma_channel_wait_params)
-#define HAILO_VDMA_CHANNEL_ABORT            _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_ABORT_CODE,         struct hailo_vdma_channel_abort_params)
-#define HAILO_VDMA_CHANNEL_CLEAR_ABORT      _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_CLEAR_ABORT_CODE,   struct hailo_vdma_channel_clear_abort_params)
-#define HAILO_VDMA_CHANNEL_READ_REGISTER    _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_READ_REGISTER_CODE, struct hailo_vdma_channel_read_register_params)
-#define HAILO_VDMA_CHANNEL_WRITE_REGISTER   _IOR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_WRITE_REGISTER_CODE, struct hailo_vdma_channel_write_register_params)
+#define HAILO_VDMA_CHANNEL_ENABLE           _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_ENABLE_CODE,         struct hailo_vdma_channel_enable_params)
+#define HAILO_VDMA_CHANNEL_DISABLE          _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_DISABLE_CODE,        struct hailo_vdma_channel_disable_params)
+#define HAILO_VDMA_CHANNEL_WAIT_INT         _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_WAIT_INT_CODE,       struct hailo_vdma_channel_wait_params)
+#define HAILO_VDMA_CHANNEL_ABORT            _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_ABORT_CODE,          struct hailo_vdma_channel_abort_params)
+#define HAILO_VDMA_CHANNEL_CLEAR_ABORT      _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_CLEAR_ABORT_CODE,    struct hailo_vdma_channel_clear_abort_params)
+#define HAILO_VDMA_CHANNEL_READ_REGISTER    _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_READ_REGISTER_CODE,  struct hailo_vdma_channel_read_register_params)
+#define HAILO_VDMA_CHANNEL_WRITE_REGISTER   _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_WRITE_REGISTER_CODE, struct hailo_vdma_channel_write_register_params)
 
 #define HAILO_VDMA_BUFFER_MAP               _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_BUFFER_MAP_CODE,            struct hailo_vdma_buffer_map_params)
 #define HAILO_VDMA_BUFFER_UNMAP             _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_BUFFER_UNMAP_CODE,          struct hailo_vdma_buffer_unmap_params)

common/hailo_pcie_version.h

@@ -7,7 +7,7 @@
 #define _HAILO_COMMON_PCIE_VERSION_H_
 
 #define HAILO_DRV_VER_MAJOR 4
-#define HAILO_DRV_VER_MINOR 10
+#define HAILO_DRV_VER_MINOR 12
 #define HAILO_DRV_VER_REVISION 0
 
 #endif /* _HAILO_COMMON_PCIE_VERSION_H_ */

common/hailo_resource.c

@@ -132,4 +132,26 @@ int hailo_resource_write_buffer(struct hailo_resource *resource, size_t offset,
     }
 
     return 0;
-}
+}
+
+int hailo_resource_transfer(struct hailo_resource *resource, struct hailo_memory_transfer_params *transfer)
+{
+    // Check for transfer size (address is in resources address-space)
+    if ((transfer->address + transfer->count) > (u64)resource->size) {
+        return -EINVAL;
+    }
+
+    if (transfer->count > ARRAY_SIZE(transfer->buffer)) {
+        return -EINVAL;
+    }
+
+    switch (transfer->transfer_direction) {
+    case TRANSFER_READ:
+        hailo_resource_read_buffer(resource, (u32)transfer->address, transfer->count, transfer->buffer);
+        return 0;
+    case TRANSFER_WRITE:
+        return hailo_resource_write_buffer(resource, (u32)transfer->address, transfer->count, transfer->buffer);
+    default:
+        return -EINVAL;
+    }
+}

common/hailo_resource.h

@@ -28,6 +28,9 @@ void hailo_resource_write8(struct hailo_resource *resource, size_t offset, uint8
 void hailo_resource_read_buffer(struct hailo_resource *resource, size_t offset, size_t count, void *to);
 int hailo_resource_write_buffer(struct hailo_resource *resource, size_t offset, size_t count, const void *from);
 
+// Transfer (read/write) the given resource into/from transfer params.
+int hailo_resource_transfer(struct hailo_resource *resource, struct hailo_memory_transfer_params *transfer);
+
 #ifdef __cplusplus
 }
 #endif