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fix #507 #632

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merged 1 commit into from
Feb 2, 2025
Merged

fix #507 #632

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2 changes: 1 addition & 1 deletion hw/vendor/pulp_platform_register_interface.lock.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/pulp-platform/register_interface.git
rev: e3a4955071fcf554febd4b29a7c7a52c7f1e7fc6
rev: 7cf6ae7d8bc14af2c83e3178e068d79271b20815
}
}
2 changes: 1 addition & 1 deletion hw/vendor/pulp_platform_register_interface.vendor.hjson
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Expand Up @@ -7,7 +7,7 @@

upstream: {
url: "https://github.com/pulp-platform/register_interface.git",
rev: "e3a4955071fcf554febd4b29a7c7a52c7f1e7fc6",
rev: "7cf6ae7d8bc14af2c83e3178e068d79271b20815",
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@davideschiavone davideschiavone Jan 31, 2025 •
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@cousteaulecommandant for next time if you would like to revendor - just you change the commit here.
Then from X-HEEP main folder you do

./util/vendor.py hw/vendor/pulp_platform_register_interface.vendor.hjson --update

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@danivz should know it :)

},

exclude_from_upstream: [
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7 changes: 6 additions & 1 deletion ...ndor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl
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Expand Up @@ -20,6 +20,11 @@
max_regs_char = len("{}".format(len(regs_flat) - 1))
addr_width = rb.get_addr_width()

# Used for the dev_select_i signal on a tlul_socket_1n with N =
# num_wins + 1. This needs to be able to represent any value up to
# N-1.
steer_msb = ((num_wins).bit_length()) - 1

lblock = block.name.lower()
ublock = lblock.upper()

Expand Down Expand Up @@ -189,7 +194,7 @@ module ${mod_name} \
% endif
% endif
% else:
logic [${num_wins_width-1}:0] reg_steer;
logic [${steer_msb}:0] reg_steer;

% if use_reg_iface:
${reg_intf_req} [${num_dsp}-1:0] reg_intf_demux_req;
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25 changes: 25 additions & 0 deletions ...ter_interface/vendor/patches/lowrisc_opentitan/reggen/0004-Backport-steer-width-fix.patch
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Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
diff --git a/reg_top.sv.tpl b/reg_top.sv.tpl
index 664e12801..3e14b553c 100644
--- a/reg_top.sv.tpl
+++ b/reg_top.sv.tpl
@@ -20,6 +20,11 @@
max_regs_char = len("{}".format(len(regs_flat) - 1))
addr_width = rb.get_addr_width()

+ # Used for the dev_select_i signal on a tlul_socket_1n with N =
+ # num_wins + 1. This needs to be able to represent any value up to
+ # N-1.
+ steer_msb = ((num_wins).bit_length()) - 1
+
lblock = block.name.lower()
ublock = lblock.upper()

@@ -189,7 +194,7 @@ module ${mod_name} \
% endif
% endif
% else:
- logic [${num_wins_width-1}:0] reg_steer;
+ logic [${steer_msb}:0] reg_steer;

% if use_reg_iface:
${reg_intf_req} [${num_dsp}-1:0] reg_intf_demux_req;