Merge remote-tracking branch 'origin/main' into feature-flash-bsp

.github/workflows/sim-apps-job/test_apps.py

@@ -24,7 +24,7 @@ class BColors:
 
 # Define parameters for the test_apps.py script
 SIMULATOR = "verilator"
-SIM_TIMEOUT_S = 120
+SIM_TIMEOUT_S = 600
 LINKER = "on_chip"
 COMPILER = "gcc"
 

.github/workflows/simulate.yml

@@ -18,5 +18,6 @@ jobs:
           make clean-all
           sed 's/is_included: "no",/is_included: "yes",/' -i mcu_cfg.hjson
           sed 's/num_channels:   0x1,/num_channels:   0x4,/' -i mcu_cfg.hjson
+          sed 's/num_channels_per_master_port: 0x1,/num_channels_per_master_port: 0x4,/' -i mcu_cfg.hjson
           make mcu-gen MEMORY_BANKS=6
           python3 .github/workflows/sim-apps-job/test_apps.py

Makefile

@@ -98,7 +98,7 @@ environment.yml: python-requirements.txt
 ## @section Installation
 
 ## Generates mcu files core-v-mini-mcu files and build the design with fusesoc
-## @param CPU=[cv32e20(default),cv32e40p,cv32e40x]
+## @param CPU=[cv32e20(default),cv32e40p,cv32e40x,cv32e40px]
 ## @param BUS=[onetoM(default),NtoM]
 ## @param MEMORY_BANKS=[2(default) to (16 - MEMORY_BANKS_IL)]
 ## @param MEMORY_BANKS_IL=[0(default),2,4,8]
@@ -193,7 +193,7 @@ questasim-sim-opt-upf: questasim-sim
 	$(MAKE) -C build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-modelsim opt-upf
 
 ## VCS simulation
-## @param CPU=cv32e20(default),cv32e40p,cv32e40x
+## @param CPU=cv32e20(default),cv32e40p,cv32e40x,cv32e40px
 ## @param BUS=onetoM(default),NtoM
 vcs-sim:
 	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=vcs $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log

configs/ci.hjson

@@ -13,11 +13,11 @@
             name: code
             start: 0
             #minimum size for freeRTOS and clang
-            size: 0x00000D800
+            size: 0x00000E800
         },
         {
             name: data
-            start: 0x00000D800
+            start: 0x00000E800
         }
     ]
 }

configs/example_interleaved.hjson

@@ -30,11 +30,11 @@
             name: code
             start: 0
             // minimum size for freeRTOS and clang
-            size: 0x00000D800
+            size: 0x00000E800
         },
         {
             name: data
-            start: 0x00000D800
+            start: 0x00000E800
         }
     ]
 }

configs/general.hjson

@@ -14,11 +14,11 @@
             name: code
             start: 0
             #minimum size for freeRTOS and clang
-            size: 0x00000D800
+            size: 0x00000E800
         },
         {
             name: data
-            start: 0x00000D800
+            start: 0x00000E800
         }
     ]
 }

configs/testall.hjson

@@ -13,11 +13,11 @@
             name: code
             start: 0
             #minimum size for freeRTOS and clang
-            size: 0x00000D800
+            size: 0x00000E800
         },
         {
             name: data
-            start: 0x00000D800
+            start: 0x00000E800
         }
     ]
 }

docs/source/How_to/eXtendingHEEP.md

@@ -2,14 +2,14 @@
 
 `X-HEEP` is meant to be extended with your own custom IPs. `X-HEEP` itself posseses a hardware-software framework capable of working standalone. If you want to extend it, you will need to merge your hardware and software with `X-HEEP`'s.
 
-For this purpose we support the [CORE-V-XIF](https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/latest/intro.html) interface with the [cv32e40x](https://github.com/openhwgroup/cv32e40x) RISCV-CPU, and we expose master and slave ports to/from the bus.
+For this purpose we support the [CV-X-IF](https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/latest/intro.html) interface with the [cv32e40x](https://github.com/openhwgroup/cv32e40x) or [cv32e40px](https://github.com/esl-epfl/cv32e40px) RISCV-CPU, and we expose master and slave ports to/from the bus.
 
-> `X-HEEP` currently uses the revision [`0.9.0`](https://github.com/openhwgroup/cv32e40x/commit/f17028f2369373d9443e4636f2826218e8d54e0f) of OpenHW Groups's `cv32e40x` core to implement the `CORE-V-XIF`. It is recommended to use the same revision in peripheral IPs to prevent conflicts during RTL compilation.
+> We recommend using the `cv32e40px` for pairing with your CV-X-IF compliant coprocessor. If you choose to use the `cv32e40x`, `X-HEEP` currently uses the revision [`0.9.0`](https://github.com/openhwgroup/cv32e40x/commit/f17028f2369373d9443e4636f2826218e8d54e0f). It is recommended to use the same revision in peripheral IPs to prevent conflicts during RTL compilation.
 
 Here you can find a list of `X-HEEP` based open-source examples. If you want to include your project in this list, please open an issue with a link to your repository.
 
 * [CGRA-X-HEEP](https://github.com/esl-epfl/cgra_x_heep): A CGRA loosely coupled with X-HEEP.
-* [F-HEEP](https://github.com/davidmallasen/F-HEEP): System integrating [fpu_ss](https://github.com/pulp-platform/fpu_ss) into X-HEEP via the eXtension interface and cv32e40x.
+* [F-HEEP](https://github.com/davidmallasen/F-HEEP): System integrating [fpu_ss](https://github.com/pulp-platform/fpu_ss) into X-HEEP via the eXtension interface and cv32e40px.
 * [KALIPSO](https://github.com/vlsi-lab/ntt_intt_kyber) and [KRONOS](https://github.com/vlsi-lab/keccak_integration/tree/keccak_xheep): Loosely-coupled, post-quantum cryptography accelerators for NTT/INTT and Keccak hash function integrated into X-HEEP.
 
 
@@ -98,7 +98,7 @@ To achieve this:
 
 * Create a new top-level repository (`BASE`) and vendorize (or add as git submodules) both your `CORE-V-XIF/OBI` compliant coprocessor/accelerator and `X-HEEP`.
 * Copy the `x-heep/hw/system/x_heep_system.sv` as your new top-level module. Then modify it as needed to include your co-processor and connect it to the `core_v_mini_mcu` with the `XIF`. The `XIF` SystemVerilog interface must be instantiated in the top-level module, where `X-HEEP` and your co-processor are connected. See the `X-HEEP` [testbench](./../../../tb/testharness.sv) as an example.
-* Before building software remember to run `make mcu-gen CPU=cv32e40x`.
+* Before building software remember to run `make mcu-gen CPU=cv32e40px`.
 
 To add this new top-level module to the simulation/synthesis flow you can extend the [FuseSoC](https://fusesoc.readthedocs.io/en/stable/user/index.html) support of `X-HEEP`.
 
@@ -328,7 +328,7 @@ include $(XHEEP_MAKE)
 * The `verilator-sim` rule will override the `X-HEEP` Makefile's one.
 * Any other target will be passed straight to `X-HEEP`'s Makefile. For example
 ```sh
-make mcu-gen CPU=cv32e40x
+make mcu-gen CPU=cv32e40px
 ```
 </details>