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fix interleaved bus (#620)
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davideschiavone authored Jan 29, 2025
1 parent 91c9e6a commit 66c7153
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Showing 2 changed files with 2 additions and 3 deletions.
1 change: 1 addition & 0 deletions hw/core-v-mini-mcu/core_v_mini_mcu.vlt
Original file line number Diff line number Diff line change
Expand Up @@ -30,3 +30,4 @@ lint_off -rule WIDTH -file "*/ao_peripheral_subsystem.sv" -match "Input port con
lint_off -rule UNDRIVEN -file "*ip/power_manager/rtl/power_manager.sv" -match "Signal is not driven: 'external_ram_banks_set_retentive*'"
lint_off -rule UNDRIVEN -file "*ip/power_manager/rtl/power_manager.sv" -match "Signal is not driven: 'external_subsystem_clkgate_en*'"
lint_off -rule UNUSED -file "*vendor/pulp_platform_register_interface/src/reg_mux.sv" -match "*"
lint_off -rule WIDTH -file "*/system_xbar.sv" -match "Operator ADD expects*"
4 changes: 1 addition & 3 deletions hw/core-v-mini-mcu/system_xbar.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -88,16 +88,14 @@ module system_xbar
end
% if xheep.has_il_ram():

localparam ZERO = 32'h0;

for (genvar j = 0; j < XBAR_NMASTER; j++) begin : gen_addr_napot
always_comb begin
port_sel[j] = pre_port_sel[j];
post_master_req_addr[j] = master_req_i[j].addr;
% for i, group in enumerate(xheep.iter_il_groups()):

if (pre_port_sel[j] == RAM_IL${i}_IDX[LOG_XBAR_NSLAVE-1:0]) begin
port_sel[j] = RAM_IL${i}_IDX[LOG_XBAR_NSLAVE-1:0] + {ZERO[LOG_XBAR_NSLAVE-${1+group.n.bit_length()}:0],master_req_i[j].addr[${group.n.bit_length()-1 +1}:2]};
port_sel[j] = RAM_IL${i}_IDX[LOG_XBAR_NSLAVE-1:0] + $unsigned(master_req_i[j].addr[${group.n.bit_length()-1 +1}:2]);
post_master_req_addr[j] = {master_req_i[j].addr[31:${2+group.n.bit_length()-1}], ${2+group.n.bit_length()-1}'h0};
end
% endfor
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