Merge pull request #3 from JoseCalero/ultrascale2

Fully update for HEEPsilon

.gitignore

@@ -4,6 +4,7 @@ build
 *.log
 *.do
 .venv/
+*__pycache__*
 # sw files
 *.map
 *.hex
@@ -12,7 +13,10 @@ build
 *.dump
 
 # ignore automatically generated files
+hw/rtl/heepsilon_pkg.sv
 tb/tb_util.svh
+sw/external/drivers/cgra/cgra.h
+
 *.vscode*
 *vivado*
 *__pycache__*

Makefile

@@ -3,7 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 
-# Makefile to generates cgra-x-heep files and build the design with fusesoc
+# Makefile to generates heepsilon files and build the design with fusesoc
 
 .PHONY: clean help
 
@@ -13,28 +13,35 @@ PORT		?= /dev/ttyUSB2
 
 # 1 external domain for the CGRA
 EXTERNAL_DOMAINS = 1
-# Use more memory banks
-MEMORY_BANKS = 4
-
-# Project options are based on the app to be build (default - hello_world)
-PROJECT  ?= hello_world
+PROJECT ?= hello_world
 
+#MEMORY_BANKS ?= 2 # Multiple of 2
+#MEMORY_BANKS_IL ?= 4 # Power of 2
+
 export HEEP_DIR = hw/vendor/esl_epfl_x_heep/
 include $(HEEP_DIR)Makefile.venv
 
+HEEPSILON_CFG  ?= heepsilon_cfg.hjson
+
+heepsilon-gen:
+	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/hw/rtl --pkg-sv hw/vendor/esl_epfl_cgra/hw/rtl/cgra_pkg.sv.tpl
+	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/hw/rtl --tpl-sv hw/vendor/esl_epfl_cgra/hw/rtl/peripheral_regs.sv.tpl
+	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/util --tpl-sv hw/vendor/esl_epfl_cgra/util/cgra_bitstream_gen.py.tpl
+	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/rtl --pkg-sv hw/rtl/heepsilon_pkg.sv.tpl
+	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir sw/external/drivers/cgra --header-c sw/external/drivers/cgra/cgra.h.tpl
+	$(PYTHON) util/heepsilon_gen.py --cfg $(HEEPSILON_CFG) --outdir hw/vendor/esl_epfl_cgra/data --pkg-sv hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson.tpl
+	bash -c "cd hw/vendor/esl_epfl_cgra/data; source cgra_reg_gen.sh; cd ../../../.."
 
 # Generates mcu files. First the mcu-gen from X-HEEP is called.
-# This is needed to be done after the X-HEEP mcu-gen because the test-bench to be used is the one from CGRA-X-HEEP, not the one from X-HEEP.
-mcu-gen:
+# This is needed to be done after the X-HEEP mcu-gen because the test-bench to be used is the one from heepsilon, not the one from X-HEEP.
+mcu-gen: heepsilon-gen
 	$(MAKE) -f $(XHEEP_MAKE) EXTERNAL_DOMAINS=${EXTERNAL_DOMAINS} MEMORY_BANKS=${MEMORY_BANKS} $(MAKECMDGOALS)
-	cd hw/vendor/esl_epfl_x_heep &&\
-	python util/mcu_gen.py --cfg mcu_cfg.hjson --pads_cfg pad_cfg.hjson  --outdir ../../../tb/ --memorybanks $(MEMORY_BANKS) --tpl-sv ../../../tb/tb_util.svh.tpl
 
 ## Builds (synthesis and implementation) the bitstream for the FPGA version using Vivado
 ## @param FPGA_BOARD=nexys-a7-100t,pynq-z2
 ## @param FUSESOC_FLAGS=--flag=<flagname>
 vivado-fpga: |venv
-	fusesoc --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup --build eslepfl:systems:cgra-x-heep 2>&1 | tee buildvivado.log
+	fusesoc --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup --build eslepfl:systems:heepsilon 2>&1 | tee buildvivado.log
 
 
 # Runs verible formating
@@ -43,24 +50,24 @@ verible:
 
 # Simulation
 verilator-sim:
-	fusesoc --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --setup --build eslepfl:systems:cgra-x-heep 2>&1 | tee buildsim.log
+	fusesoc --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --setup --build eslepfl:systems:heepsilon 2>&1 | tee buildsim.log
 
 questasim-sim:
-	fusesoc --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --setup --build eslepfl:systems:cgra-x-heep 2>&1 | tee buildsim.log
+	fusesoc --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --setup --build eslepfl:systems:heepsilon 2>&1 | tee buildsim.log
 
 questasim-sim-opt: questasim-sim
-	$(MAKE) -C build/eslepfl_systems_cgra-x-heep_0/sim-modelsim opt
+	$(MAKE) -C build/eslepfl_systems_heepsilon_0/sim-modelsim opt
 
 vcs-sim:
-	fusesoc --cores-root . run --no-export --target=sim --tool=vcs $(FUSESOC_FLAGS) --setup --build eslepfl:systems:cgra-x-heep 2>&1 | tee buildsim.log
+	fusesoc --cores-root . run --no-export --target=sim --tool=vcs $(FUSESOC_FLAGS) --setup --build eslepfl:systems:heepsilon 2>&1 | tee buildsim.log
 
 
 ## Generates the build output for a given application
 ## Uses verilator to simulate the HW model and run the FW
 ## UART Dumping in uart0.log to show recollected results
 run-verilator:
 	$(MAKE) app PROJECT=$(PROJECT)
-	cd ./build/eslepfl_systems_cgra-x-heep_0/sim-verilator; \
+	cd ./build/eslepfl_systems_heepsilon_0/sim-verilator; \
 	./Vtestharness +firmware=../../../sw/build/main.hex; \
 	cat uart0.log; \
 	cd ../../..;
@@ -70,7 +77,7 @@ run-verilator:
 ## UART Dumping in uart0.log to show recollected results
 run-questasim:
 	$(MAKE) app PROJECT=$(PROJECT)
-	cd ./build/eslepfl_systems_cgra-x-heep_0/sim-modelsim; \
+	cd ./build/eslepfl_systems_heepsilon_0/sim-modelsim; \
 	make run PLUSARGS="c firmware=../../../sw/build/main.hex"; \
 	cat uart0.log; \
 	cd ../../..;

README.md

@@ -17,7 +17,7 @@ Due to its modular design, HEEPsilon respects the X-HEEP workflow. As such, you
 
 Althought the HEEPsilon team will try to keep the latest version of X-HEEP available, changes in the X-HEEP setup might not reflect immediately on this repository.
 
-👉 For the most accurate set-up instructions please refer to the documentation of the [vendorized X-HEEP](https://github.com/esl-epfl/cgra_x_heep/tree/main/hw/vendor/esl_epfl_x_heep).
+👉 For the most accurate set-up instructions please refer to the documentation of the [vendorized X-HEEP](https://github.com/esl-epfl/heepsilon/tree/main/hw/vendor/esl_epfl_x_heep).
 
 
 # Behavioural simulations

cgra_x_heep.core → heepsilon.core

@@ -4,8 +4,8 @@ CAPI=2:
 # Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
-name: eslepfl:systems:cgra-x-heep
-description: CGRA X-HEEP Top.
+name: eslepfl:systems:heepsilon
+description: HEEPsilon (X-HEEP + CGRA) Top.
 
 filesets:
   files_rtl_generic:
@@ -14,8 +14,8 @@ filesets:
     - openhwgroup.org:systems:core-v-mini-mcu
     - eslepfl::cgra
     files:
-    - hw/rtl/cgra_x_heep_pkg.sv
-    - hw/rtl/cgra_x_heep_top.sv
+    - hw/rtl/heepsilon_pkg.sv
+    - hw/rtl/heepsilon_top.sv
     file_type: systemVerilogSource
 
   x_heep_system:
@@ -97,25 +97,26 @@ filesets:
     file_type: systemVerilogSource
 
   rtl-fpga:
+    depend:
+    - openhwgroup.org:systems:core-v-mini-mcu-fpga
     files:
-    - hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
-    - hw/fpga/sram_wrapper.sv
-    - hw/fpga_cgra/cgra_sram_wrapper.sv
-    - hw/fpga_cgra/cgra_clock_gate.sv
-    - hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv
-    file_type: systemVerilogSource
+    - hw/fpga_cgra/scripts/generate_sram_general.tcl: { file_type: tclSource }
+    - hw/fpga_cgra/scripts/generate_sram_emem.tcl: { file_type: tclSource }
+    - hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/cgra_sram_wrapper.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/cgra_clock_gate.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/xilinx_heepsilon_wrapper.sv:  { file_type: systemVerilogSource }
 
-  ip-fpga:
+  xdc-fpga-pynq-z2:
     files:
-    - hw/fpga/scripts/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
-    - hw/fpga/scripts/generate_sram.tcl:  { file_type: tclSource }
-    - hw/fpga/prim_xilinx_clk.sv:  { file_type: systemVerilogSource } # Here there are the following modules
-    - hw/fpga/cve2_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_input_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_output_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_inout_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_bypass_input_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_bypass_output_xilinx.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc
+    - hw/fpga/constraints/pynq-z2/constraints.xdc
+    file_type: xdc
+
+  xdc-fpga-zcu104:
+    files:
+    - hw/fpga_cgra/constraints/zcu104/pin_assign.xdc
+    file_type: xdc
 
   fpga-arm-emulation:
     depend:
@@ -127,33 +128,71 @@ filesets:
     - linux_femu/constraints/pin_assign.xdc: {file_type: xdc}
     - linux_femu/constraints/constraints.xdc: {file_type: xdc}
 
-  xdc-fpga-pynq-z2:
-    files:
-    - hw/fpga_cgra/constraints/pin_assign.xdc
-    file_type: xdc
-
-  netlist-fpga:
-    files:
-    - build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v
-    file_type: verilogSource
-
 parameters:
   COREV_PULP:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables COREV_PULP custom RISC-V extension on the CV32E40P core. Admitted values: 1|0.
+    default: 0
+  FPU:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables RV32F RISC-V extension on the CV32E40P core. Admitted values: 1|0.
     default: 0
   JTAG_DPI:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables testbench JTAG DIPs. Admitted values: 1|0.
     default: 0
+  X_EXT:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables CORE-V-XIF interface for the CV32E40X and CV32E40PX cores. Admitted values: 1|0.
+    default: 0
+  USE_EXTERNAL_DEVICE_EXAMPLE:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables testbench modules compilation. Admitted values: 1|0.
+    default: 1
   USE_UPF:
     datatype: bool
     paramtype: vlogdefine
-    default: false
+    description: |
+      Enables simulation with UPF with Modelsim/VCS
+  REMOVE_OBI_FIFO:
+    datatype: bool
+    paramtype: vlogdefine
+    description: |
+      Remove the FIFO between the BUS and the peripherals subsystems
   SYNTHESIS:
     datatype: bool
     paramtype: vlogdefine
     default: false
+  VERILATOR: #used by SV2V
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  SIM_SYSTEMC:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_NEXYS:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_ZCU104:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
   # Make the parameter known to FuseSoC to enable overrides from the
   # command line. If not overwritten, use the generic technology library.
   PRIM_DEFAULT_IMPL:
@@ -179,7 +218,7 @@ targets:
   default: &default_target
     filesets:
     - files_rtl_generic
-    toplevel: [cgra_x_heep_top]
+    toplevel: [heepsilon_top]
 
   sim:
     <<: *default_target
@@ -266,15 +305,43 @@ targets:
     description: TUL Pynq-Z2 Board
     filesets_append:
     - x_heep_system
-    - files_rtl_generic # Already added by default?
     - rtl-fpga
-    - ip-fpga
     - xdc-fpga-pynq-z2
     - ext_bus
     parameters:
-    - COREV_PULP=0
+    - COREV_PULP
+    - FPU
+    - X_EXT
     - SYNTHESIS=true
+    - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
     tools:
       vivado:
         part: xc7z020clg400-1
-    toplevel: [xilinx_cgra_x_heep_wrapper]
+        board_part: tul.com.tw:pynq-z2:part0:1.0
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_pynq_z2_board_files]
+    toplevel: [xilinx_heepsilon_wrapper]
+
+  zcu104:
+    <<: *default_target
+    default_tool: vivado
+    description: ZCU104 Evaluation Board
+    filesets_append:
+    - x_heep_system
+    - rtl-fpga
+    - xdc-fpga-zcu104
+    - ext_bus
+    parameters:
+    - COREV_PULP
+    - FPU
+    - X_EXT
+    - SYNTHESIS=true
+    - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
+    - FPGA_ZCU104=true
+    tools:
+      vivado:
+        part: xczu7ev-ffvc1156-2-e
+        board_part: xilinx.com:zcu104:part0:1.0
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files]
+    toplevel: [xilinx_heepsilon_wrapper]

heepsilon_cfg.hjson

@@ -0,0 +1,32 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Derived from Occamy: https://github.com/pulp-platform/snitch/blob/master/hw/system/occamy/src/occamy_cfg.hjson
+// Peripherals configuration for core-v-mini-mcu.
+{
+    cgra: {
+        // Main impact: more columns equals more master ports connected to the bus
+        // There is a maximum limit because of the kernel configuration size fixed to the bus width of 32 bits
+        // This limit can be increased but manual changes are required
+        // Maximum number of columns: 32-log2(rcs_num_instr)-log2(max_columns*rcs_num_instr)
+        // Default settings enable: 32-log2(32)-log2(4*32) = 20 columns
+        num_columns: 4
+        // Main impact: more rows equals to more context memory banks (i.e., one per row)
+        // There should be no limitation compared to the number of rows compared to columns
+        num_rows: 4
+        // It is possible to limit the maximum number of columns a kernel can use (this saves a bit of resources)
+        // The default value should be the same than num_columns, put an number to change it
+        max_columns: default
+        // Number of instructions each RC can contain (usually a power of 2)
+        rcs_num_instr: 32
+        // Context memory bank depth
+        // This parameter is by default set to max_columns*rcs_num_instr
+        // The default depth correspond to a minimum required in case a kernel uses max_columns and rcs_num_instr instructions per RC
+        // The depth can be increased in case more kernels need to be stored inside the context memory
+        cmem_bk_depth: default
+        // This value fixes the maximum number of kernel configuration words that can be stores
+        // It does not mean that the context memory can holds that many kernels, it depends on the size of each kernel
+        // You probably don't need to change this value
+        kmem_depth: 16
+    },
+}