Add spike RISC-V simulator support

config/riscv32/boards/spike/board.cfg

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+# Board configuration for riscv-isa-sim (spike
+#
+# Copyright (C) 2022 Embecosm Limited and University of Bristol
+#
+# Contributor TODO
+#
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+# This is a python setting of parameters for the board.  The following
+# parameters may be set (other keys are silently ignored).  Defaults are shown
+# in brackets
+# cc = 'riscv32-unknown-elf-gcc'
+# - ld (same value as for cc)
+# cflags = (['-c', '-Os', '-ffunction-sections', '-nostdlib', '-march=rv32imac', '-mabi=ilp32'])
+# ldflags = (['-Wl,-gc-sections', '-nostdlib', '-march=rv32imac', '-mabi=ilp32', '-T../../../config/riscv32/boards/rv32wallyverilog/link.ld'])
+# cflags = (['-c', '-Os', '-ffunction-sections', '-nostartfiles', '-march=rv32imac', '-mabi=ilp32'])
+# ldflags = (['-Wl,-gc-sections', '-nostartfiles', '-march=rv32imac', '-mabi=ilp32', '-T../../../config/riscv32/boards/rv32wallyverilog/link.ld'])
+cflags = (['-c', '-march=rv32imafdc', '-mabi=ilp32d', '-DSPIKE'])
+ldflags = (['-march=rv32imafdc', '-mabi=ilp32d', '-T../../../config/riscv32/boards/spike/link.ld'])
+# - cc_define_pattern ('-D{0}')
+# - cc_incdir_pattern ('-I{0}')
+# - cc_input_pattern ('{0}')
+# - cc_output_pattern ('-o {0}')
+# - ld_input_pattern ('{0}')
+# - ld_output_pattern ('-o {0}')
+user_libs = (['-lc'])
+# dummy_libs = (['libm'])
+# dummy_libs = (['libgcc', 'libm', 'libc'])
+# - cpu_mhz (1)
+# - warmup_heat (1)
+
+# The "flags" and "libs" parameters (cflags, ldflags, user_libs, dummy_libs)
+# should be lists of arguments to be passed to the compile or link line as
+# appropriate.  Patterns are Python format patterns used to create arguments.
+# Thus for GCC or Clang/LLVM defined constants can be passed using the prefix
+# '-D', and the pattern '-D{0}' would be appropriate (which happens to be the
+# default).
+
+# "user_libs" may be absolute file names or arguments to the linker. In the
+# latter case corresponding arguments in ldflags may be needed.  For example
+# with GCC or Clang/LLVM is "-l" flags are used in "user_libs", the "-L" flags
+# may be needed in "ldflags".
+
+# Dummy libs have their source in the "support" subdirectory. Thus if 'crt0'
+# is specified, there should be a source file 'dummy-crt0.c' in the support
+# directory.
+
+# There is no need to set an unused parameter, and this file may be empty to
+# set no flags.
+
+# Parameter values which are duplicated in architecture, board, chip or
+# command line are used in the following order of priority
+# - default value
+# - architecture specific value
+# - chip specific value
+# - board specific value
+# - command line value
+
+# For flags, this priority is applied to individual flags, not the complete
+# list of flags.
+
+cpu_mhz = 1

config/riscv32/boards/spike/boardsupport.c

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+/* Copyright HighTec EDV-Systeme GmbH 2023
+
+   This file is part of Embench.
+
+   SPDX-License-Identifier: GPL-3.0-or-later OR Apache-2.0 */
+
+#include <stdio.h>
+
+unsigned long long start;
+extern void _exit(int i);
+
+#define CORETIMETYPE unsigned long long
+#define read_csr(reg) ({ unsigned long __tmp; \
+    asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+    __tmp; })
+
+
+void __attribute__ ((noinline)) __attribute__ ((externally_visible))
+start_trigger ()
+{
+    unsigned long hi = read_csr(mcycleh);
+    unsigned long lo = read_csr(mcycle);
+    start = (unsigned long long)(((CORETIMETYPE)hi) << 32) | lo;
+}
+
+void __attribute__ ((noinline)) __attribute__ ((externally_visible))
+stop_trigger ()
+{
+    unsigned long hi = read_csr(mcycleh);
+    unsigned long lo = read_csr(mcycle);
+    unsigned long long end = (unsigned long long)(((CORETIMETYPE)hi) << 32) | lo;
+    printf("Spike mcycle timer delta: %llu\n", end - start);
+}
+
+void __attribute__ ((noinline))
+initialise_board ()
+{
+}

config/riscv32/boards/spike/crt0.S

@@ -0,0 +1,67 @@
+/* Startup code for spike RISC-V ISA simulator with FPU enabled
+
+   Copyright (C) 2017  SiFive Inc. All rights reserved.
+
+   This file is part of Embench.
+
+   SPDX-License-Identifier: GPL-3.0-or-later OR BSD-2-Clause */
+
+; #include "newlib.h"
+
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+
+#=========================================================================
+# crt0.S : Entry point for RISC-V user programs
+#=========================================================================
+
+  .text
+  .global _start
+  .type   _start, @function
+  .section .text.startup
+_start:
+  # Initialize global pointer
+.option push
+.option norelax
+1:auipc gp, %pcrel_hi(__global_pointer$)
+  addi  gp, gp, %pcrel_lo(1b)
+.option pop
+
+  # enable FPU and accelerator if present
+  li t0, MSTATUS_FS | MSTATUS_XS
+  csrs mstatus, t0
+
+  # Clear the bss segment
+  la      sp, __ram_end__ 
+  la      a0, __bss_start__
+  la      a2, _end
+  sub     a2, a2, a0
+  li      a1, 0
+  call    memset
+#ifdef HAS_ATEXIT
+#ifdef _LITE_EXIT
+  # Make reference to atexit weak to avoid unconditionally pulling in
+  # support code.  Refer to comments in __atexit.c for more details.
+  .weak   atexit
+  la      a0, atexit
+  beqz    a0, .Lweak_atexit
+  .weak   __libc_fini_array
+#endif
+
+  la      a0, __libc_fini_array   # Register global termination functions
+  call    atexit                  #  to be called upon exit
+#ifdef _LITE_EXIT
+.Lweak_atexit:
+#endif
+#endif
+  call    __libc_init_array       # Run global initialization functions
+
+  #lw      a0, 0(sp)                  # a0 = argc
+  #addi    a1, sp, __SIZEOF_POINTER__ # a1 = argv
+  #li      a2, 0                      # a2 = envp = NULL
+  li a0, 0
+  li a1, 0
+  li a2, 0
+  call    main
+  tail    exit
+  .size  _start, .-_start

config/riscv32/boards/spike/link.ld

@@ -0,0 +1,93 @@
+/* Linker script for spike RISC-V ISA simulator
+
+   Copyright (C) 2014-2020 Free Software Foundation, Inc.
+
+   This file is part of Embench.
+
+   SPDX-License-Identifier: GPL-3.0-or-later OR FSFAP */
+
+OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
+OUTPUT_ARCH(riscv)
+
+MEMORY
+{
+   /* qemu-system-risc32 virt machine */
+   RAM (rwx)  : ORIGIN = 0x80000000, LENGTH = 1M 
+}
+
+ENTRY(_start) /* this will cause an error if the symbol _start is not present */
+
+SECTIONS
+{
+	. = ORIGIN(RAM);
+
+	PROVIDE(__ram_origin__ = ORIGIN(RAM));
+	PROVIDE(__ram_end__ = ORIGIN(RAM) + LENGTH(RAM));
+
+	.text.startup : { *(.text.startup) }
+	. = ALIGN(0x1000);
+	.tohost : { *(.htif) }
+	. = ALIGN(0x1000);
+	.text : { *(.text*) }
+	. = ALIGN(0x1000);
+
+	/*. = ALIGN(0x10);*/	/* putting this here does not cause the followng section to move */
+
+	.rodata : /*ALIGN(0x10):*/	/* this will the align section but others can overlap */
+	{
+		. = ALIGN(0x10);		/* aligning here will align the section & update the loc counter */
+		__rodata_start = .;
+		*(.rodata.*)
+		*(.srodata.*)
+		__rodata_end = .;
+	}
+
+	.data : 
+	{ 
+		. = ALIGN(0x1000);
+		__data_start = .;
+		*(.data.*) 
+		*(.sdata*) 				/* small data objects */
+		__data_end = .; 
+	}
+
+    __global_pointer$ = (__data_start + 0x800);	/* stick this somewhere potentially useful */
+
+
+/**/
+  .preinit_array    :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  }
+  .init_array    :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  }
+  .fini_array    :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  }
+/**/
+
+	.bss : 
+	{
+		. = ALIGN(0x100);
+		__bss_start  = .;
+		__bss_start__ = .;
+		*(.sbss*) 			/* small data objects */
+		*(.bss*) 
+		__bss_end = .;
+		__bss_end__ = .;
+	}
+
+	_end = .; 
+}
+

config/riscv32/boards/spike/ns16550.h

@@ -0,0 +1,41 @@
+/* RISC-V rv32 tutorial examples
+
+   Copyright (C) 2021 John Winans
+
+   This file is part of Embench.
+
+   SPDX-License-Identifier: GPL-3.0-or-later */
+
+
+#ifndef ns16550_H
+#define ns16550_H
+
+#include <stdint.h>
+
+// inferred from the qemu-system-riscv32 dtb values
+#define NS16550_THR	(*((volatile uint8_t *)0x10000000))
+#define NS16550_RBR	(*((volatile uint8_t *)0x10000000))
+#define NS16550_IER	(*((volatile uint8_t *)0x10000001))
+#define NS16550_IIR	(*((volatile uint8_t *)0x10000002))
+#define NS16550_FCR	(*((volatile uint8_t *)0x10000002))
+#define NS16550_LCR	(*((volatile uint8_t *)0x10000003))
+#define NS16550_MCR	(*((volatile uint8_t *)0x10000004))
+#define NS16550_LSR	(*((volatile uint8_t *)0x10000005))
+#define NS16550_MSR	(*((volatile uint8_t *)0x10000006))
+#define NS16550_SCR	(*((volatile uint8_t *)0x10000007))
+
+#define NS16550_LSR_THRE	(1<<5)
+
+/**
+* Wait for the TX FIFO to have room for a byte and send it.
+***************************************************************************/
+inline __attribute__((always_inline)) void ns16550_tx(uint8_t ch)
+{
+	// be careful about order of operations here...
+	while((NS16550_LSR & NS16550_LSR_THRE) == 0)
+		;
+	NS16550_THR = ch;
+}
+
+#endif
+