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add AHB verification to the CI
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M0stafaRady committed Feb 29, 2024
1 parent 9e8cc40 commit 524d839
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Showing 3 changed files with 57 additions and 9 deletions.
55 changes: 54 additions & 1 deletion .github/workflows/uvm_ci.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ on:
pull_request: # This now triggers on pull requests to any branch

jobs:
test_and_clean:
verify_APB:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
Expand Down Expand Up @@ -56,6 +56,59 @@ jobs:
with:
name: failed_tests
path: verify/uvm-python/failed_tests.tar.gz

verify_AHB:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2

- name: Set up Python
uses: actions/setup-python@v2
with:
python-version: '3.x'

- name: download docker
run: |
docker pull efabless/dv:cocotb
- name: Navigate to verify/uvm-python and run tests
run: |
cd verify/uvm-python
make run_all_tests RUN_MERGE_COVERAGE=false BUS_TYPE=AHB
- name: Check for test results in run
run: |
cd verify/uvm-python
passed_count=$(find sim/default_tag -type f -name 'passed' | wc -l)
failed_count=$(find sim/default_tag -type f -name 'failed' | wc -l)
unknown_count=$(find sim/default_tag -type f -name 'unknown' | wc -l)
echo "Passed: $passed_count"
echo "Failed: $failed_count"
echo "Unknown: $unknown_count"
if [ "$passed_count" -eq 0 ]; then
echo "Error: No passed test results found"
exit 1
elif [ "$failed_count" -ne 0 ] || [ "$unknown_count" -ne 0 ]; then
echo "Error: There are failed or unknown test results"
exit 1
else
echo "All tests passed successfully"
fi
- name: tar failed tests
if: failure()
run: |
cd verify/uvm-python
tar -czf failed_tests.tar.gz sim/default_tag
- name: upload failed tests
if: failure()
uses: actions/upload-artifact@v2
with:
name: failed_tests
path: verify/uvm-python/failed_tests.tar.gz

lint: # Lint the RTL code
runs-on: ubuntu-latest
steps:
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2 changes: 0 additions & 2 deletions verify/uvm-python/test_lib.py
Original file line number Diff line number Diff line change
Expand Up @@ -54,8 +54,6 @@
async def module_top(dut):
# profiler = cProfile.Profile()
# profiler.enable()
arr = []
# sv.value_plusargs('BUS_TYPE',arr)
BUS_TYPE = cocotb.plusargs['BUS_TYPE']
print(f"plusr agr value = {BUS_TYPE}")
pif = uart_if(dut)
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9 changes: 3 additions & 6 deletions verify/uvm-python/top.v
Original file line number Diff line number Diff line change
Expand Up @@ -3,18 +3,17 @@
module top();
reg CLK = 0;
wire RESETn = 1;
wire RX;
wire TX;
wire irq;
`ifdef BUS_TYPE_APB
wire RX;
wire TX;

wire [31:0] PADDR;
wire PWRITE;
wire PSEL;
wire PENABLE;
wire [31:0] PWDATA;
wire [31:0] PRDATA;
wire PREADY;
wire irq;
EF_UART_APB dut(.rx(RX), .tx(TX), .PCLK(CLK), .PRESETn(RESETn), .PADDR(PADDR), .PWRITE(PWRITE), .PSEL(PSEL), .PENABLE(PENABLE), .PWDATA(PWDATA), .PRDATA(PRDATA), .PREADY(PREADY), .IRQ(irq));
`endif // BUS_TYPE_APB
`ifdef BUS_TYPE_AHB
Expand All @@ -26,7 +25,6 @@ module top();
wire [31:0] HWDATA;
wire [31:0] HRDATA;
wire HREADY;
wire irq;
EF_UART_AHBL dut(.rx(RX), .tx(TX), .HCLK(CLK), .HRESETn(RESETn), .HADDR(HADDR), .HWRITE(HWRITE), .HSEL(HSEL), .HTRANS(HTRANS), .HWDATA(HWDATA), .HRDATA(HRDATA), .HREADY(HREADY),.HREADYOUT(HREADYOUT), .IRQ(irq));
`endif // BUS_TYPE_AHB
`ifdef BUS_TYPE_WISHBONE
Expand All @@ -37,7 +35,6 @@ module top();
wire cyc_i;
wire stb_i;
reg ack_o;
wire we_i;
EF_UART_wb dut(.rx(RX), .tx(TX), .clk_i(CLK), .rst_i(~rst_i), .adr_i(adr_i), .dat_i(dat_i), .dat_o(dat_o), .sel_i(sel_i), .cyc_i(cyc_i), .stb_i(stb_i), .ack_o(ack_o),.we_i(we_i), .irq(irq));
`endif // BUS_TYPE_WISHBONE
// monitor inside signals
Expand Down

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