use bus_seq_base in the sequences that uses the bus

verify/uvm-python/uart_seq_lib/uart_rx_read.py

@@ -6,28 +6,32 @@
 from EF_UVM.bus_env.bus_item import bus_item
 from uvm.base.uvm_config_db import UVMConfigDb
 import random
+from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
 
 
-class uart_rx_read(UVMSequence):
+class uart_rx_read(bus_seq_base):
 
     def __init__(self, name="uart_rx_read"):
-        UVMSequence.__init__(self, name)
-        self.set_automatic_phase_objection(1)
-        self.req = bus_item()
-        self.rsp = bus_item()
+        super().__init__(name)
         self.tag = name
 
     async def body(self):
         # get register names/address conversion dict
         arr = []
-        if (not UVMConfigDb.get(self, "", "bus_regs", arr)):
+        if not UVMConfigDb.get(self, "", "bus_regs", arr):
             uvm_fatal(self.tag, "No json file wrapper regs")
         else:
             adress_dict = arr[0].reg_name_to_address
         # randomly config uart
         # first disabled the uart
         for _ in range(random.randint(1, 18)):
-            await uvm_do_with(self, self.req, lambda addr: addr == adress_dict["RXDATA"], lambda kind: kind == bus_item.READ, lambda data: data == 0)
+            await uvm_do_with(
+                self,
+                self.req,
+                lambda addr: addr == adress_dict["RXDATA"],
+                lambda kind: kind == bus_item.READ,
+                lambda data: data == 0,
+            )
             # await uvm_do_with(self, self.req, lambda addr: addr == adress_dict["im"], lambda kind: kind == bus_item.WRITE, lambda data: data == 0)
 
 

verify/uvm-python/uart_seq_lib/uart_tx_seq.py

@@ -1,4 +1,3 @@
-from uvm.seq import UVMSequence
 from uvm.macros.uvm_object_defines import uvm_object_utils
 from uvm.macros.uvm_message_defines import uvm_info, uvm_fatal
 from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do
@@ -9,26 +8,32 @@
 import os
 import random
 from uart_seq_lib.uart_config import uart_config
+from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
 
 
-class uart_tx_seq(UVMSequence):
+class uart_tx_seq(bus_seq_base):
 
     def __init__(self, name="uart_tx_seq"):
-        UVMSequence.__init__(self, name)
-        self.set_automatic_phase_objection(1)
-        self.req = bus_item()
-        self.rsp = bus_item()
+        super().__init__(name)
         self.tag = name
 
     async def body(self):
-        # configure uart 
+        # configure uart
         config_seq = uart_config("uart_config")
         await uvm_do(self, config_seq)  # change the presclar
         for _ in range(30):
             random_send = random.randint(1, 16)
             for __ in range(random_send):
-                await uvm_do_with(self, self.req, lambda addr: addr == 0x4, lambda kind: kind == bus_item.WRITE, lambda data: data in range(0, 0x200))
-            for __ in range(random.randint(0, random_send-1 if random_send > 1 else 1)):
+                await uvm_do_with(
+                    self,
+                    self.req,
+                    lambda addr: addr == 0x4,
+                    lambda kind: kind == bus_item.WRITE,
+                    lambda data: data in range(0, 0x200),
+                )
+            for __ in range(
+                random.randint(0, random_send - 1 if random_send > 1 else 1)
+            ):
                 await self.monitor.tx_received.wait()
                 self.monitor.tx_received.clear()