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update uart wrappers
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@M0stafaRady
M0stafaRady committed Sep 30, 2024
1 parent ea31861 commit 3c995b3
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Showing 6 changed files with 201 additions and 52 deletions.
26 changes: 25 additions & 1 deletion hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,10 @@ module EF_UART_AHBL #(
GFLEN = 8,
FAW = 4
) (




input wire HCLK,
input wire HRESETn,
input wire HWRITE,
Expand Down Expand Up @@ -138,7 +142,21 @@ module EF_UART_AHBL #(
localparam MIS_REG_OFFSET = 16'hFF04;
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;
wire clk = HCLK;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(HCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = HRESETn;


Expand Down Expand Up @@ -264,6 +282,11 @@ module EF_UART_AHBL #(
else
TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;

localparam GCLK_REG_OFFSET = 16'hFF10;
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0;
else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET))
GCLK_REG <= HWDATA[1-1:0];

reg [9:0] IM_REG;
reg [9:0] IC_REG;
reg [9:0] RIS_REG;
Expand Down Expand Up @@ -387,6 +410,7 @@ module EF_UART_AHBL #(
(last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
(last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
(last_HADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG :
(last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;

assign HREADYOUT = 1'b1;
Expand Down
24 changes: 23 additions & 1 deletion hdl/rtl/bus_wrappers/EF_UART_AHBL.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,10 @@ module EF_UART_AHBL #(
GFLEN = 8,
FAW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif
`AHBL_SLAVE_PORTS,
input wire [1-1:0] rx,
output wire [1-1:0] tx
Expand All @@ -54,7 +58,21 @@ module EF_UART_AHBL #(
localparam MIS_REG_OFFSET = `AHBL_AW'hFF04;
localparam RIS_REG_OFFSET = `AHBL_AW'hFF08;
localparam IC_REG_OFFSET = `AHBL_AW'hFF0C;
wire clk = HCLK;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk(HCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
)

wire clk = clk_g;
wire rst_n = HRESETn;


Expand Down Expand Up @@ -144,6 +162,9 @@ module EF_UART_AHBL #(
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
`AHBL_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)

localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10;
`AHBL_REG(GCLK_REG, 0, 1)

reg [9:0] IM_REG;
reg [9:0] IC_REG;
reg [9:0] RIS_REG;
Expand Down Expand Up @@ -262,6 +283,7 @@ module EF_UART_AHBL #(
(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
(last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;

assign HREADYOUT = 1'b1;
Expand Down
118 changes: 93 additions & 25 deletions hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,81 @@

`timescale 1ns/1ps
`default_nettype none



/*
Copyright 2020 AUCOHL
Author: Mohamed Shalan ([email protected])
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at:
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
























































module EF_UART_APB #(
parameter
Expand All @@ -29,10 +104,10 @@ module EF_UART_APB #(
GFLEN = 8,
FAW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif




input wire PCLK,
input wire PRESETn,
input wire PWRITE,
Expand Down Expand Up @@ -65,27 +140,20 @@ module EF_UART_APB #(
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];

`ifdef FPGA
wire clk = PCLK;
`else
(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
`endif
.GCLK(clk_g),
.GATE(clk_gated_en),
.CLK(PCLK)
);

wire clk = clk_g;
`endif
reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(PCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = PRESETn;


Expand Down
35 changes: 14 additions & 21 deletions hdl/rtl/bus_wrappers/EF_UART_APB.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -59,27 +59,20 @@ module EF_UART_APB #(
localparam RIS_REG_OFFSET = `APB_AW'hFF08;
localparam IC_REG_OFFSET = `APB_AW'hFF0C;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];

`ifdef FPGA
wire clk = PCLK;
`else
(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
`endif
.GCLK(clk_g),
.GATE(clk_gated_en),
.CLK(PCLK)
);

wire clk = clk_g;
`endif
reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk(PCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
)

wire clk = clk_g;
wire rst_n = PRESETn;


Expand Down
27 changes: 24 additions & 3 deletions hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,10 @@ module EF_UART_WB #(
GFLEN = 8,
FAW = 4
) (




input wire ext_clk,
input wire clk_i,
input wire rst_i,
Expand All @@ -95,8 +99,8 @@ module EF_UART_WB #(
output reg ack_o,
input wire we_i,
output wire IRQ,
input wire [1-1:0] rx,
output wire [1-1:0] tx
input wire [1-1:0] rx,
output wire [1-1:0] tx
);

localparam RXDATA_REG_OFFSET = 16'h0000;
Expand All @@ -115,7 +119,21 @@ module EF_UART_WB #(
localparam MIS_REG_OFFSET = 16'hFF04;
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;
wire clk = clk_i;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(clk_i),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = (~rst_i);


Expand Down Expand Up @@ -208,6 +226,9 @@ module EF_UART_WB #(
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
always @(posedge clk_i or posedge rst_i) if(rst_i) TX_FIFO_FLUSH_REG <= 0; else if(wb_we & (adr_i[16-1:0]==TX_FIFO_FLUSH_REG_OFFSET)) TX_FIFO_FLUSH_REG <= dat_i[1-1:0]; else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;

localparam GCLK_REG_OFFSET = 16'hFF10;
always @(posedge clk_i or posedge rst_i) if(rst_i) GCLK_REG <= 0; else if(wb_we & (adr_i[16-1:0]==GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];

reg [9:0] IM_REG;
reg [9:0] IC_REG;
reg [9:0] RIS_REG;
Expand Down
23 changes: 22 additions & 1 deletion hdl/rtl/bus_wrappers/EF_UART_WB.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,10 @@ module EF_UART_WB #(
GFLEN = 8,
FAW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif
`WB_SLAVE_PORTS,
input wire [1-1:0] rx,
output wire [1-1:0] tx
Expand All @@ -54,7 +58,21 @@ module EF_UART_WB #(
localparam MIS_REG_OFFSET = `WB_AW'hFF04;
localparam RIS_REG_OFFSET = `WB_AW'hFF08;
localparam IC_REG_OFFSET = `WB_AW'hFF0C;
wire clk = clk_i;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk(clk_i),
.clk_en(clk_gated_en),
.clk_o(clk_g)
)

wire clk = clk_g;
wire rst_n = (~rst_i);


Expand Down Expand Up @@ -144,6 +162,9 @@ module EF_UART_WB #(
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
`WB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)

localparam GCLK_REG_OFFSET = `WB_AW'hFF10;
`WB_REG(GCLK_REG, 0, 1)

reg [9:0] IM_REG;
reg [9:0] IC_REG;
reg [9:0] RIS_REG;
Expand Down

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