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update reset sequence calling
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M0stafaRady committed Mar 13, 2024
1 parent 8303474 commit 09eea27
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Showing 10 changed files with 20 additions and 49 deletions.
2 changes: 1 addition & 1 deletion verify/uvm-python/ref_model/ref_model.py
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ def connect_phase(self, phase):

def write_bus(self, tr):
uvm_info(self.tag, "Vip write: " + tr.convert2string(), UVM_MEDIUM)
if tr.reset:
if tr.kind == bus_item.RESET:
self.model.reset()
self.bus_bus_export.write(tr)
return
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4 changes: 2 additions & 2 deletions verify/uvm-python/uart_scoreboard.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
from uvm.comps import UVMScoreboard
from uvm.macros import uvm_component_utils, uvm_info
from uvm.base.uvm_object_globals import UVM_MEDIUM, UVM_LOW
from uvm.base.uvm_object_globals import UVM_HIGH, UVM_LOW
from uart_item.uart_item import uart_item
from EF_UVM.scoreboard import scoreboard

Expand All @@ -14,7 +14,7 @@ def __init__(self, name="uart_scoreboard", parent=None):

def write_ip(self, tr):
# filter the ip checker to check only the TX, RX ones are checked by reading the register
uvm_info(self.tag, "write_ip: " + tr.convert2string(), UVM_MEDIUM)
uvm_info(self.tag, "write_ip: " + tr.convert2string(), UVM_HIGH)
if tr.direction == uart_item.TX:
self.q_ip.put_nowait(tr)

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7 changes: 3 additions & 4 deletions verify/uvm-python/uart_seq_lib/rx_length_parity_seq.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,7 @@
from uvm.macros.uvm_sequence_defines import uvm_do_with
from uvm.base import sv, UVM_HIGH, UVM_LOW
import random
from uart_seq_lib.seq_base import seq_base
from EF_UVM.bus_env.bus_seq_lib.reset_seq import reset_seq
from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do
from uart_seq_lib.uart_config import uart_config
from uvm.seq import UVMSequence
Expand Down Expand Up @@ -32,7 +31,7 @@ async def body(self):
await NextTimeStep() # wait dummy delay until event is clear


class rx_length_parity_seq_wrapper(seq_base):
class rx_length_parity_seq_wrapper(bus_seq_base):
def __init__(self, handshake_event, name="rx_length_parity_seq_wrapper"):
super().__init__(name)
self.handshake_event = handshake_event
Expand All @@ -43,7 +42,7 @@ def __init__(self, handshake_event, name="rx_length_parity_seq_wrapper"):

async def body(self):
for length, parity in self.all_comb:
await uvm_do(self, reset_seq())
await self.send_reset()
config = length | (parity << 5) | (random.randint(0, 1) << 4) | 0x3F << 8
await uvm_do(self, uart_config(im=0, config=config))
self.handshake_event.set()
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27 changes: 0 additions & 27 deletions verify/uvm-python/uart_seq_lib/seq_base.py

This file was deleted.

7 changes: 3 additions & 4 deletions verify/uvm-python/uart_seq_lib/tx_length_parity_seq.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,15 +3,14 @@
from uvm.base import sv, UVM_HIGH, UVM_LOW
from EF_UVM.bus_env.bus_item import bus_item
import random
from uart_seq_lib.seq_base import seq_base
from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
from uvm.macros.uvm_message_defines import uvm_info, uvm_fatal
from EF_UVM.bus_env.bus_seq_lib.reset_seq import reset_seq
from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do
from uart_seq_lib.uart_config import uart_config
from uart_seq_lib.tx_seq import tx_seq


class tx_length_parity_seq(seq_base):
class tx_length_parity_seq(bus_seq_base):
def __init__(self, name="tx_length_parity_seq"):
super().__init__(name)
lengths = [5, 6, 7, 8, 9]
Expand All @@ -22,7 +21,7 @@ def __init__(self, name="tx_length_parity_seq"):

async def body(self):
for length, parity in self.all_comb:
await uvm_do(self, reset_seq())
await self.send_reset()
config = length | (parity << 5) | (random.randint(0, 1) << 4) | 0x3F << 8
await uvm_do(self, uart_config(im=0, config=config))
await uvm_do(self, self.tx_seq_obj)
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4 changes: 2 additions & 2 deletions verify/uvm-python/uart_seq_lib/tx_seq.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,10 @@
from uvm.base import sv, UVM_HIGH, UVM_LOW
from EF_UVM.bus_env.bus_item import bus_item
import random
from uart_seq_lib.seq_base import seq_base
from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base


class tx_seq(seq_base):
class tx_seq(bus_seq_base):
def __init__(self, name="tx_seq", repeat=1):
super().__init__(name)
self.repeat = repeat
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4 changes: 2 additions & 2 deletions verify/uvm-python/uart_seq_lib/uart_config.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,10 @@
from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do
from uvm.base import sv, UVM_HIGH, UVM_LOW
from EF_UVM.bus_env.bus_item import bus_item
from uart_seq_lib.seq_base import seq_base
from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base


class uart_config(seq_base):
class uart_config(bus_seq_base):
def __init__(self, name="uart_config", prescaler=None, config=None, im=None, match=None, fifo_control=None, control=None):
super().__init__(name)
self.prescaler = prescaler
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4 changes: 2 additions & 2 deletions verify/uvm-python/uart_seq_lib/uart_loopback_seq.py
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,10 @@
import os
import random
from uart_seq_lib.uart_config import uart_config
from uart_seq_lib.seq_base import seq_base
from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base


class uart_loopback_seq(seq_base):
class uart_loopback_seq(bus_seq_base):
def __init__(self, name="uart_loopback_seq"):
super().__init__(name)

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7 changes: 3 additions & 4 deletions verify/uvm-python/uart_seq_lib/uart_prescalar_seq.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,8 @@
from uvm.base import sv, UVM_HIGH, UVM_LOW
from uart_item.uart_item import uart_item
import random
from uart_seq_lib.seq_base import seq_base
from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
from uart_seq_lib.uart_config import uart_config
from EF_UVM.bus_env.bus_seq_lib.reset_seq import reset_seq
from uart_seq_lib.tx_seq import tx_seq
from uart_seq_lib.rx_seq import rx_seq
from cocotb.triggers import NextTimeStep
Expand All @@ -31,7 +30,7 @@ async def body(self):
self.handshake_event.set()


class uart_prescalar_seq_wrapper(seq_base):
class uart_prescalar_seq_wrapper(bus_seq_base):

def __init__(self, handshake_event, name="uart_prescalar_seq_wrapper"):
super().__init__(name)
Expand All @@ -46,7 +45,7 @@ async def body(self):
# reset then set new prescalar
for prescaler_val in self.prescaler_vals:
uvm_info(self.get_type_name(), f"prescaler_val = {prescaler_val}", UVM_LOW)
await uvm_do(self, reset_seq())
await self.send_reset()
await uvm_do(self, uart_config(im=0, prescaler=prescaler_val))
self.handshake_event.set()
await uvm_do(self, self.tx_seq_obj)
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3 changes: 2 additions & 1 deletion verify/uvm-python/uart_seq_lib/uart_tx_seq.py
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,8 @@
import os
import random
from uart_seq_lib.uart_config import uart_config
from EF_UVM.bus_env.bus_seq_lib.reset_seq import reset_seq


class uart_tx_seq(UVMSequence):

def __init__(self, name="uart_tx_seq"):
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