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use new base test format
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@M0stafaRady
M0stafaRady committed Apr 15, 2024
1 parent 1b9a7ba commit 015ad47
Showing 1 changed file with 53 additions and 97 deletions.
150 changes: 53 additions & 97 deletions verify/uvm-python/test_lib.py
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Original file line number Diff line number Diff line change
Expand Up @@ -9,20 +9,32 @@
from uvm.base.uvm_globals import run_test
from EF_UVM.top_env import top_env
from uart_interface.uart_if import uart_if
from EF_UVM.bus_env.bus_interface.bus_if import bus_apb_if, bus_irq_if, bus_ahb_if, bus_wb_if
from EF_UVM.bus_env.bus_interface.bus_if import (
bus_apb_if,
bus_irq_if,
bus_ahb_if,
bus_wb_if,
)
from cocotb_coverage.coverage import coverage_db
from cocotb.triggers import Event, First
from EF_UVM.bus_env.bus_regs import bus_regs
from uvm.base.uvm_report_server import UVMReportServer

# seq
from EF_UVM.bus_env.bus_seq_lib.write_read_regs import write_read_regs
from uart_seq_lib.uart_tx_seq import uart_tx_seq
from uart_seq_lib.uart_config import uart_config
from uart_seq_lib.uart_rx_read import uart_rx_read
from uart_seq_lib.uart_rx_seq import uart_rx_seq
from uart_seq_lib.tx_length_parity_seq import tx_length_parity_seq
from uart_seq_lib.rx_length_parity_seq import rx_length_parity_seq, rx_length_parity_seq_wrapper
from uart_seq_lib.uart_prescalar_seq import uart_prescalar_seq_wrapper, uart_prescalar_seq
from uart_seq_lib.rx_length_parity_seq import (
rx_length_parity_seq,
rx_length_parity_seq_wrapper,
)
from uart_seq_lib.uart_prescalar_seq import (
uart_prescalar_seq_wrapper,
uart_prescalar_seq,
)
from uart_seq_lib.uart_loopback_seq import uart_loopback_seq
from uvm.base import UVMRoot

Expand All @@ -40,21 +52,22 @@
from EF_UVM.ip_env.ip_logger.ip_logger import ip_logger
from uart_logger.uart_logger import uart_logger

#
#
from EF_UVM.bus_env.bus_agent.bus_ahb_driver import bus_ahb_driver
from EF_UVM.bus_env.bus_agent.bus_apb_driver import bus_apb_driver
from EF_UVM.bus_env.bus_agent.bus_wb_driver import bus_wb_driver
from EF_UVM.bus_env.bus_agent.bus_ahb_monitor import bus_ahb_monitor
from EF_UVM.bus_env.bus_agent.bus_apb_monitor import bus_apb_monitor
from EF_UVM.bus_env.bus_agent.bus_wb_monitor import bus_wb_monitor

from EF_UVM.base_test import base_test


@cocotb.test()
async def module_top(dut):
# profiler = cProfile.Profile()
# profiler.enable()
BUS_TYPE = cocotb.plusargs['BUS_TYPE']
BUS_TYPE = cocotb.plusargs["BUS_TYPE"]
print(f"plusr agr value = {BUS_TYPE}")
pif = uart_if(dut)
if BUS_TYPE == "APB":
Expand All @@ -69,7 +82,9 @@ async def module_top(dut):
UVMConfigDb.set(None, "*", "ip_if", pif)
UVMConfigDb.set(None, "*", "bus_if", w_if)
UVMConfigDb.set(None, "*", "bus_irq_if", w_irq_if)
UVMConfigDb.set(None, "*", "json_file", "/home/rady/work/uvm_unit/EF_UART/EF_UART.json")
UVMConfigDb.set(
None, "*", "json_file", "/home/rady/work/uvm_unit/EF_UART/EF_UART.json"
)
yaml_file = []
UVMRoot().clp.get_arg_values("+YAML_FILE=", yaml_file)
yaml_file = yaml_file[0]
Expand All @@ -88,110 +103,51 @@ async def module_top(dut):
# profiler.dump_stats("profile_result.prof")




class base_test(UVMTest):
def __init__(self, name="base_test", parent=None):
super().__init__(name, parent)
self.test_pass = True
self.top_env = None
self.printer = None
class uart_base_test(base_test):
def __init__(self, name="uart_base_test", parent=None):
BUS_TYPE = cocotb.plusargs["BUS_TYPE"]
super().__init__(name, bus_type=BUS_TYPE, parent=parent)
self.tag = name

def build_phase(self, phase):
# UVMConfigDb.set(self, "example_tb0.bus_env.bus_agent.bus_sequencer.run_phase", "default_sequence", write_seq.type_id.get())
super().build_phase(phase)
# override
# override
self.set_type_override_by_type(ip_driver.get_type(), uart_driver.get_type())
self.set_type_override_by_type(ip_monitor.get_type(), uart_monitor.get_type())
self.set_type_override_by_type(ref_model.get_type(), UART_VIP.get_type())
self.set_type_override_by_type(scoreboard.get_type(), uart_scoreboard.get_type())
self.set_type_override_by_type(
scoreboard.get_type(), uart_scoreboard.get_type()
)
self.set_type_override_by_type(ip_coverage.get_type(), uart_coverage.get_type())
self.set_type_override_by_type(ip_logger.get_type(), uart_logger.get_type())
BUS_TYPE = cocotb.plusargs['BUS_TYPE']
if BUS_TYPE == "AHB":
self.set_type_override_by_type(bus_apb_driver.get_type(), bus_ahb_driver.get_type())
self.set_type_override_by_type(bus_apb_monitor.get_type(), bus_ahb_monitor.get_type())
elif BUS_TYPE == "WISHBONE":
self.set_type_override_by_type(bus_apb_driver.get_type(), bus_wb_driver.get_type())
self.set_type_override_by_type(bus_apb_monitor.get_type(), bus_wb_monitor.get_type())
# self.set_type_override_by_type(ip_item.get_type(),uart_item.get_type())
# Enable transaction recording for everything
UVMConfigDb.set(self, "*", "recording_detail", UVM_FULL)
# Create the tb
self.example_tb0 = top_env.type_id.create("example_tb0", self)
# Create a specific depth printer for printing the created topology
self.printer = UVMTablePrinter()
self.printer.knobs.depth = -1

arr = []
if UVMConfigDb.get(None, "*", "ip_if", arr) is True:
UVMConfigDb.set(self, "*", "ip_if", arr[0])
else:
uvm_fatal("NOVIF", "Could not get ip_if from config DB")

if UVMConfigDb.get(None, "*", "bus_if", arr) is True:
UVMConfigDb.set(self, "*", "bus_if", arr[0])
else:
uvm_fatal("NOVIF", "Could not get bus_if from config DB")
# set max number of uvm errors
server = UVMReportServer()
server.set_max_quit_count(3)
UVMCoreService.get().set_report_server(server)


def end_of_elaboration_phase(self, phase):
# Set verbosity for the bus monitor for this demo
uvm_info(self.get_type_name(), sv.sformatf("Printing the test topology :\n%s", self.sprint(self.printer)), UVM_LOW)

def start_of_simulation_phase(self, phase):
self.bus_sqr = self.example_tb0.bus_env.bus_agent.bus_sequencer
self.ip_sqr = self.example_tb0.ip_env.ip_agent.ip_sequencer

async def run_phase(self, phase):
uvm_info("sequence", "Starting test", UVM_LOW)

def extract_phase(self, phase):
super().check_phase(phase)
server = UVMCoreService.get().get_report_server()
errors = server.get_severity_count(UVM_ERROR)
if errors > 0:
uvm_fatal("FOUND ERRORS", "There were " + str(errors) + " UVM_ERRORs in the test")

def report_phase(self, phase):
uvm_info(self.get_type_name(), "report_phase", UVM_LOW)
if self.test_pass:
uvm_info(self.get_type_name(), "** UVM TEST PASSED **", UVM_LOW)
else:
uvm_fatal(self.get_type_name(), "** UVM TEST FAIL **\n" +
self.err_msg)


uvm_component_utils(base_test)


class TX_StressTest(base_test):


uvm_component_utils(uart_base_test)


class TX_StressTest(uart_base_test):
def __init__(self, name="TX_StressTest", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
bus_seq = uart_tx_seq("uart_tx_seq")
bus_seq.monitor = self.example_tb0.ip_env.ip_agent.monitor
bus_seq.monitor = self.top_env.ip_env.ip_agent.monitor
await bus_seq.start(self.bus_sqr)
phase.drop_objection(self, f"{self.__class__.__name__} drop objection")


uvm_component_utils(TX_StressTest)


class RX_StressTest(base_test):
class RX_StressTest(uart_base_test):
def __init__(self, name="RX_StressTest", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
ip_seq_rx = uart_rx_seq("uart_rx_seq")
Expand All @@ -207,35 +163,35 @@ async def run_phase(self, phase):
uvm_component_utils(RX_StressTest)


class LoopbackTest(base_test):
class LoopbackTest(uart_base_test):
def __init__(self, name="LoopbackTest", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
bus_seq = uart_loopback_seq("uart_loopback_seq")
bus_seq.monitor = self.example_tb0.ip_env.ip_agent.monitor
bus_seq.monitor = self.top_env.ip_env.ip_agent.monitor
await bus_seq.start(self.bus_sqr)
phase.drop_objection(self, f"{self.__class__.__name__} drop objection")


uvm_component_utils(LoopbackTest)


class PrescalarStressTest(base_test):
class PrescalarStressTest(uart_base_test):
def __init__(self, name="PrescalarTest", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
handshake_event = Event("handshake_event")
ip_seq = uart_prescalar_seq(handshake_event)
bus_seq = uart_prescalar_seq_wrapper(handshake_event)
bus_seq.tx_seq_obj.monitor = self.example_tb0.ip_env.ip_agent.monitor
bus_seq.tx_seq_obj.monitor = self.top_env.ip_env.ip_agent.monitor
bus_seq_thread = await cocotb.start(bus_seq.start(self.bus_sqr))
ip_seq_thread = await cocotb.start(ip_seq.start(self.ip_sqr))
await First(ip_seq_thread, bus_seq_thread)
Expand All @@ -245,29 +201,29 @@ async def run_phase(self, phase):
uvm_component_utils(PrescalarStressTest)


class LengthParityTXStressTest(base_test):
class LengthParityTXStressTest(uart_base_test):
def __init__(self, name="LengthParityTXStressTest", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
bus_seq = tx_length_parity_seq()
bus_seq.tx_seq_obj.monitor = self.example_tb0.ip_env.ip_agent.monitor
bus_seq.tx_seq_obj.monitor = self.top_env.ip_env.ip_agent.monitor
await bus_seq.start(self.bus_sqr)
phase.drop_objection(self, f"{self.__class__.__name__} drop objection")


uvm_component_utils(LengthParityTXStressTest)


class LengthParityRXStressTest(base_test):
class LengthParityRXStressTest(uart_base_test):
def __init__(self, name="LengthParityRXStressTest", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
handshake_event = Event("handshake_event")
Expand All @@ -282,12 +238,12 @@ async def run_phase(self, phase):
uvm_component_utils(LengthParityRXStressTest)


class WriteReadRegsTest(base_test):
class WriteReadRegsTest(uart_base_test):
def __init__(self, name="WriteReadRegsTest", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
bus_seq = write_read_regs()
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