Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

x86 Add parallel bits extract/deposit instructions #7392

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

x86 Add parallel bits extract/deposit instructions #7392

wants to merge 1 commit into from

Conversation

BradleyWood
Copy link
Contributor

No description provided.

@0xdaryl
Copy link
Contributor

0xdaryl commented Sep 12, 2024

Jenkins build xlinux,win,xmac

@0xdaryl
Copy link
Contributor

0xdaryl commented Sep 12, 2024

@BradleyWood : see CI test failure

@BradleyWood
Copy link
Contributor Author

Cannot use legacy SSE encoding for 3-operand instruction

std::make_tuple(TR::InstOpCode::PEXT4RegRegReg, TR::RealRegister::eax, TR::RealRegister::ecx, TR::RealRegister::edx, OMR::X86::Default, "c4e272f5c2"),

So this instruction is not a SIMD instruction but uses the VEX prefix. I need to think about what to do about this scenario.

@BradleyWood BradleyWood mentioned this pull request Oct 3, 2024
Open
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@0xdaryl 0xdaryl Awaiting requested review from 0xdaryl 0xdaryl is a code owner

@mstoodle mstoodle Awaiting requested review from mstoodle mstoodle is a code owner

Assignees

@0xdaryl 0xdaryl

Labels
arch:x86 comp:compiler comp:test
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@BradleyWood @0xdaryl