Merge pull request #314 from c0d3z3r0/for-upstream/fake-tristate-relax

i2c: relax the bus after epilog in fake-tristate mode

pyftdi/i2c.py

@@ -965,6 +965,12 @@ def _clk_lo_data_lo(self) -> Tuple[int]:
                 self._gpio_low,
                 self.I2C_DIR | (self._gpio_dir & 0xFF))
 
+    @property
+    def _clk_input_data_input(self) -> Tuple[int]:
+        return (Ftdi.SET_BITS_LOW,
+                self._gpio_low,
+                (self._gpio_dir & 0xFF))
+
     @property
     def _idle(self) -> Tuple[int]:
         return (Ftdi.SET_BITS_LOW,
@@ -1037,6 +1043,9 @@ def _do_prolog(self, i2caddress: int) -> None:
     def _do_epilog(self) -> None:
         self.log.debug('   epilog')
         cmd = bytearray(self._stop)
+        if self._fake_tristate:
+            # SCL high-Z, SDA high-Z
+            cmd.extend(self._clk_input_data_input)
         self._ftdi.write_data(cmd)
         # be sure to purge the MPSSE reply
         self._ftdi.read_data_bytes(1, 1)