Change: syntax update to pass Quartus synthesis

dpretet · Feb 12, 2024 · ddf3ede · ddf3ede
1 parent 5245260
commit ddf3ede
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Showing 13 changed files with 78 additions and 45 deletions.
diff --git a/rtl/friscv_bus_perf.sv b/rtl/friscv_bus_perf.sv
@@ -26,7 +26,10 @@ module friscv_bus_perf
         output logic [NB_BUS*REG_W*3 -1:0] perfs
     );
 
-    for (genvar i=0;i<NB_BUS;i++) begin
+    genvar i;
+
+    generate
+    for (i=0;i<NB_BUS;i++) begin: PERF_CNTRS
 
         always @ (posedge aclk or negedge aresetn) begin
             if (!aresetn) begin
@@ -46,6 +49,7 @@ module friscv_bus_perf
             end
         end
     end
+    endgenerate
 
 endmodule
 

diff --git a/rtl/friscv_cache_block_fetcher.sv b/rtl/friscv_cache_block_fetcher.sv
@@ -83,9 +83,9 @@ module friscv_cache_block_fetcher
 
     // Control fsm, the sequencer driving the cache read and the memory controller
     typedef enum logic[1:0] {
-        IDLE = 0,
-        LOAD = 1,
-        FETCH = 2
+        IDLE  = 2'h0,
+        LOAD  = 2'h1,
+        FETCH = 2'h2
     } seq_fsm;
 
     seq_fsm loader, loader_prev;

diff --git a/rtl/friscv_cache_flusher.sv b/rtl/friscv_cache_flusher.sv
@@ -59,9 +59,9 @@ module friscv_cache_flusher
     localparam MAX_CACHE_ADDR = CACHE_DEPTH << $clog2(CACHE_BLOCK_W/8);
 
     typedef enum logic[1:0] {
-        IDLE = 0,
-        FLUSH = 1,
-        ACK = 2
+        IDLE  = 2'h0,
+        FLUSH = 2'h1,
+        ACK   = 2'h2
     } ctrl_fsm;
 
     ctrl_fsm cfsm;

diff --git a/rtl/friscv_cache_ooo_mgt.sv b/rtl/friscv_cache_ooo_mgt.sv
@@ -129,6 +129,9 @@ module friscv_cache_ooo_mgt
     logic [AXI_ID_W-1:0] cpl1_id_m;
     logic [AXI_ID_W-1:0] cpl2_id_m;
 
+    genvar i;
+
+
     ////////////////////////////////////////////////////////////////////////////////
     // AXI4-lite completions
     ////////////////////////////////////////////////////////////////////////////////
@@ -154,9 +157,10 @@ module friscv_cache_ooo_mgt
     assign tag_avlb = (tags[2*req_tag_pt+:2] == FREE);
     assign next_tag = req_tag_pt | AXI_ID_MASK;
 
-    for (genvar i=0; i<NB_TAG; i=i+1) begin
+    generate
+    for (i=0; i<NB_TAG; i=i+1) begin : TAGS_META_COMPLETION
 
-        always @ (posedge aclk or negedge aresetn) begin
+        always @ (posedge aclk or negedge aresetn) begin: TAGS
             if (!aresetn) begin
                 tags[2*i+:2] <= FREE;
             end else if (srst) begin
@@ -192,7 +196,7 @@ module friscv_cache_ooo_mgt
         end
 
         // Stores the ID to give back on completion
-        always @ (posedge aclk or negedge aresetn) begin
+        always @ (posedge aclk or negedge aresetn) begin: META
             if (!aresetn) begin
                 meta_ram[i] <= {AXI_ID_W{1'b0}};
             end else if (srst) begin
@@ -207,7 +211,7 @@ module friscv_cache_ooo_mgt
         end
 
         // Stores the completion data/resp to give back on completion
-        always @ (posedge aclk or negedge aresetn) begin
+        always @ (posedge aclk or negedge aresetn) begin: COMPLETION
             if (!aresetn) begin
                 if (CPL_PAYLOAD)
                     cpl_ram[i] <= {2'b0, {XLEN{1'b0}}};
@@ -232,6 +236,7 @@ module friscv_cache_ooo_mgt
             end
         end
     end
+    endgenerate
 
     ////////////////////////////////////////////////////////////////////////////////
     // Pointer management for request and completion
@@ -281,6 +286,7 @@ module friscv_cache_ooo_mgt
         logic [2   -1:0] cpl_resp;
 
         assign to_cpl = tags[2*cpl_tag_pt+CPL];
+
         if (CPL_PAYLOAD) begin
             assign cpl_data = cpl_ram[cpl_tag_pt][0+:XLEN];
             assign cpl_resp = cpl_ram[cpl_tag_pt][XLEN+:2];

diff --git a/rtl/friscv_cache_prefetcher.sv b/rtl/friscv_cache_prefetcher.sv
@@ -80,9 +80,9 @@ module friscv_cache_prefetcher
 
     // Control fsm, the sequencer driving the cache read and the memory controller
     typedef enum logic[1:0] {
-        IDLE = 0,
-        LOAD = 1,
-        FETCH = 2
+        IDLE  = 2'h0,
+        LOAD  = 2'h1,
+        FETCH = 2'h2
     } seq_fsm;
 
     seq_fsm loader;

diff --git a/rtl/friscv_cache_pusher.sv b/rtl/friscv_cache_pusher.sv
@@ -120,6 +120,8 @@ module friscv_cache_pusher
     logic                       awready;
     logic                       wready;
 
+    genvar i;
+
     // Tracer setup
     `ifdef TRACE_CACHE
     string fname;
@@ -294,7 +296,8 @@ module friscv_cache_pusher
 
     // Track the outstanding request to drive back completion to the application
     // FIXME: can't track a cache miss and an IO req in the same cycle
-    for (genvar i=0; i<OSTDREQ_NUM; i=i+1) begin : ID_TRACKER
+    generate
+    for (i=0; i<OSTDREQ_NUM; i=i+1) begin : ID_TRACKER
 
         always @ (posedge aclk or negedge aresetn) begin
             if (!aresetn) begin
@@ -312,6 +315,7 @@ module friscv_cache_pusher
             end
         end
     end
+    endgenerate
 
     // TODO: manage back-pressure of completion channel readiness
     // Today OoO or memfy are always ready

diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv
@@ -138,13 +138,13 @@ module friscv_control
 
     // Control fsm
     typedef enum logic[3:0] {
-        BOOT    = 0,
-        FETCH   = 1,
-        RELOAD  = 2,
-        FENCE   = 3,
-        FENCE_I = 4,
-        WFI     = 5,
-        EBREAK  = 6
+        BOOT    = 4'h0,
+        FETCH   = 4'h1,
+        RELOAD  = 4'h2,
+        FENCE   = 4'h3,
+        FENCE_I = 4'h4,
+        WFI     = 4'h5,
+        EBREAK  = 4'h6
     } pc_fsm;
 
     pc_fsm cfsm;

diff --git a/rtl/friscv_dcache.sv b/rtl/friscv_dcache.sv
@@ -437,6 +437,7 @@ module friscv_dcache
     ///////////////////////////////////////////////////////////////////////////
 
 
+    generate
     if (IO_MAP_NB > 0) begin: RD_OOO_INSTANCE
 
     friscv_cache_ooo_mgt
@@ -487,6 +488,7 @@ module friscv_dcache
     );
 
     end
+    endgenerate
 
     ///////////////////////////////////////////////////////////////////////////
     // Write block management

diff --git a/rtl/friscv_io_subsystem.sv b/rtl/friscv_io_subsystem.sv
@@ -78,10 +78,10 @@ module friscv_io_subsystem
 
     // Control fsm
     typedef enum logic[1:0] {
-        IDLE = 0,
-        WAIT_WDATA = 1,
-        WAIT_BRESP = 2,
-        WAIT_RRESP = 3
+        IDLE = 2'h0,
+        WAIT_WDATA = 2'h1,
+        WAIT_BRESP = 2'h2,
+        WAIT_RRESP = 2'h3
     } axi4l_fsm;
 
 

diff --git a/rtl/friscv_m_ext.sv b/rtl/friscv_m_ext.sv
@@ -113,10 +113,16 @@ module friscv_m_ext
         end
     end
 
-    for (genvar i=0;i<NB_INT_REG;i++) begin
+    generate
+
+    genvar i;
+
+    for (i=0;i<NB_INT_REG;i++) begin : RESERVATION
         assign m_regs_sts[i] = regs_or[i] == '0;
     end
 
+    endgenerate
+
 
     ///////////////////////////////////////////////////////////////////////////
     //

diff --git a/rtl/friscv_memfy.sv b/rtl/friscv_memfy.sv
@@ -195,13 +195,15 @@ module friscv_memfy
     logic                           stall_bus;
 
     typedef enum logic[1:0] {
-        IDLE = 0,
-        WAIT = 1,
-        SERVE = 2
+        IDLE  = 2'h0,
+        WAIT  = 2'h1,
+        SERVE = 2'h2
     } seq_fsm;
 
     seq_fsm state;
 
+    genvar i;
+
     ///////////////////////////////////////////////////////////////////////////
     //
     // Instruction bus fields
@@ -396,8 +398,8 @@ module friscv_memfy
                         state <= SERVE;
                         arvalid <= 1'b1;
                     end else if (opcode_r==`STORE && !waiting_rd_cpl) begin
-                        state <= SERVE;
-                        awvalid <= 1'b1;
+                            state <= SERVE;
+                            awvalid <= 1'b1;
                         wvalid <= 1'b1;
                     end
                 end
@@ -470,7 +472,10 @@ module friscv_memfy
         end
     end
 
-    for (genvar i=1;i<NB_INT_REG;i++) begin
+    generate
+
+
+    for (i=1;i<NB_INT_REG;i++) begin : REG_RESERVATION
         always @ (posedge aclk or negedge aresetn) begin
             if (!aresetn) begin
                 regs_or[i] <= '0;
@@ -491,10 +496,12 @@ module friscv_memfy
         end
     end
 
-    for (genvar i=0;i<NB_INT_REG;i++) begin
+    for (i=0;i<NB_INT_REG;i++) begin : NO_RESERVATION
         assign memfy_regs_sts[i] = regs_or[i] == '0;
     end
 
+    endgenerate
+
 
     ////////////////////////////////////////////////////////////////////////
     //
@@ -627,7 +634,7 @@ module friscv_memfy
 
     if (IO_MAP_NB > 0) begin : IO_MAP_DEC
 
-        for (genvar i=0;i<IO_MAP_NB;i=i+1) begin : GEN_IO_HIT
+        for (i=0;i<IO_MAP_NB;i=i+1) begin : GEN_IO_HIT
             assign io_map_hit[i] = (addr>=IO_MAP[i*2*XLEN+:XLEN] && addr<=IO_MAP[i*2*XLEN+XLEN+:XLEN]);
         end
 

diff --git a/rtl/friscv_mpu.sv b/rtl/friscv_mpu.sv
@@ -59,10 +59,10 @@ module friscv_mpu
 
     // Address matching A field encoding
     typedef enum logic[1:0] {
-        OFF    = 0,
-        TOR    = 1,
-        NA4    = 2,
-        NAPOT  = 3
+        OFF    = 2'h0,
+        TOR    = 2'h1,
+        NA4    = 2'h2,
+        NAPOT  = 2'h3
     } ADDR_MATCH;
 
     // The Sv32 page-based virtual-memory supports 34-bit physical addresses for RV32
@@ -90,7 +90,11 @@ module friscv_mpu
     // PMP / PMA circuits
     /////////////////////////////////////////////////////////////////////////////////////////
 
-    generate if (MPU_SUPPORT==0) begin: MPU_OFF
+    generate 
+
+    genvar i;
+
+    if (MPU_SUPPORT==0) begin: MPU_OFF
 
     assign imem_pmp_matchs = '0;
     assign imem_match = 1'b0;
@@ -105,7 +109,7 @@ module friscv_mpu
     end else begin: MPU_ON
 
         // Region addres decoding from PMPCFG+PMPADDR CSRs
-        for (genvar i=0; i<MAX_PMP_REGION; i++) begin: PMP_REGION_CHECKERS
+        for (i=0; i<MAX_PMP_REGION; i++) begin: PMP_REGION_CHECKERS
 
             if (i<NB_PMP_REGION) begin: REGION_ACTIVE
 
@@ -138,7 +142,7 @@ module friscv_mpu
         // imem / dmem PMP address match
         ////////////////////////////////
 
-        for (genvar i=0; i<MAX_PMP_REGION; i++) begin: PMP_ACCESS_CHECK
+        for (i=0; i<MAX_PMP_REGION; i++) begin: PMP_ACCESS_CHECK
 
             if (i<NB_PMP_REGION) begin: REGION_ACTIVE
 

diff --git a/rtl/friscv_uart.sv b/rtl/friscv_uart.sv
@@ -40,9 +40,9 @@ module friscv_uart
     ///////////////////////////////////////////////////////////////////////////
 
     typedef enum logic[3:0] {
-        IDLE = 0,
-        XFER = 1,
-        RWFIFO = 2
+        IDLE   = 4'h0,
+        XFER   = 4'h1,
+        RWFIFO = 4'h2
     } xfer_fsm;
 
     xfer_fsm rxfsm;