Fix: enclose function around ifdef to avoid yosys synthesis error

dpretet · Sep 3, 2023 · 8db0518 · 8db0518
1 parent d98d5d0
commit 8db0518
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/rtl/friscv_registers.sv b/rtl/friscv_registers.sv
@@ -76,6 +76,7 @@ module friscv_registers
         input  wire  [XLEN                -1:0] csr_rd_val
     );
 
+    `ifdef TRACE_REGISTERS
     //------------------------------------------------
     // Function to print register name and information
     // @i: register number to get info
@@ -116,6 +117,7 @@ module friscv_registers
         if (i==30) get_name = "  t5    (temporary register 5)";
         if (i==31) get_name = "  t6    (temporary register 6)";
     endfunction
+    `endif
 
 
     // E extension limiting the register number to 16