Fix: divisor module asserted its ready one cycle earlier, making the RD

     register not updated yet during a back-to-back processing
New: Add printf benchmark

README.md

@@ -21,6 +21,7 @@ FRISCV is a SystemVerilog implementation of the [RISCV ISA](https://riscv.org):
 - Support Zifencei
 - Support Zicsr
 - Support Zicntr
+- Support Zihpm
 - Support M extension (multiply/divide)
 - Machine-mode only
 - Implement a 3-stage pipeline

doc/project_mgt_hw.md

@@ -1,5 +1,28 @@
+# Planning: Next big topics
+
+- [-] Enhance globally performance
+- [ ] User & supervisor modes
+- [ ] 64bits support
+- [ ] Atomic ops
+- [ ] F extension
+- [ ] Division enhancement
+
 # DOING
 
+Mesure et amélioration des performances
+- [ ] Print et save des registres CSRs pour chaque test, garde la trace des performances dans Git
+- [ ] Ajouter d’autres compteurs de performances pour les processing et caches
+- [ ] point de mesure des différents bus en bandwidth et latence pour les reqs et completions
+    - [ ] min & max
+    - [ ] moyenne
+    - [ ] Écart type
+- [ ] CPI
+- [ ] Enhance read outstanding requests in MemFy et OoO
+- [ ] Augmenter le nombre d’OR max de dCache 
+- [ ] Reduce cache jump
+- [ ] Branch prediction
+- [ ] Cache ooo queue vs compteur
+
 # BACKLOG
 
 N.B. :
@@ -17,11 +40,12 @@ Cache Stage Enhancement:
 - [ ] Support datapath adaptation from memory controller
     - Narrow transfer support?
     - Gather/merge multiple continuous transactions?
+- [ ] Cache OoO manager to use queue vs compteur
 
 Misc.
+- [ ] Random peripheral
 - [ ] Support cache disable in testbench
 - [ ] Put in place profiling
-- [ ] Add Zihpm
 - [ ] Print des tests qui ne marchent pas dans le bash et svut_h.sv pour verilator
 - [ ] Rework pipeline to avoid double not
 - [ ] 64 bits support
@@ -56,6 +80,13 @@ AXI4 Infrastructure
 - [ ] Implement a L2 cache stage
 - [ ] Ooo write completion, response needs to come from the destination if IO write
 
+dCache - OoO off
+- [ ] Voir le memory model et fence
+- [ ] Serait applicable si le processeur est OoO
+- [ ] Handled by app
+- [ ] IDs must be issued from 0
+- [ ] IDs must be all different
+- [ ] Out-of-order in memfy
 
 Control:
 - [ ] Detect IO requests to forward info for FENCE execution
@@ -115,6 +146,8 @@ Hardware Test:
 
 # DONE
 
+- [X] Add Zihpm
+- [X] Fix TX read of UART which is blocking
 - [X] Develop dCache
     - [X] Uncachable access for IOs region
     - [X] Derive from iCache

doc/project_mgt_sw.md

@@ -8,13 +8,16 @@ C app
     - [ ] EIP SIP générée depuis le cpp
     - [ ] https://mullerlee.cyou/2020/07/09/riscv-exception-interrupt/#How-to-run-my-code
 - [ ] Micro kermel
+- [ ] Pool arena / malloc
 - [ ] Unit test framework
-- [ ] Binary tree
 - [ ] Sorting (bitonic)
 - [ ] Matrix computation
 - [ ] Neural network like layer
 - [ ] Binary tree
-- [ ] Msgpk like library 
+- [ ] Msgpk like library
+- [ ] Graphic tests and rendering
+    - Generate images and convert in ASCII
+    - fractal: https://en.m.wikipedia.org/wiki/Menger_sponge
 - [ ] Tiny tracer
     - [ ] https://github.com/Naitsirc98/Tiny-Ray-Tracer
     - [ ] https://github.com/ssloy/tinyraytracer
@@ -26,7 +29,11 @@ Misc.
 
 - [ ] Testsuite Rust https://danielmangum.com/posts/risc-v-bytes-rust-cross-compilation/
 - [ ] Testsuite Go
-
+- [ ] Jeu utilisant le moins de KB possible
+    - [ ] Lldvelh
+    - [ ] Zelda like
+    - [ ] Casse tête
+    - [ ] 2048
 
 
 Minimalistic Unix
@@ -51,7 +58,7 @@ Minimalistic Unix
     - [ ] https://github.com/riscv-software-src/riscv-tests
     - [ ] Run SPEC benchmark
     - [ ] Run NBench
-    - [ ] https://github.com/darklife/darkriscv/tree/master/src/coremark 
+    - [ ] https://github.com/darklife/darkriscv/tree/master/src/coremark
 - [ ] Code Pong with AI for auto game
 - [ ] Run Doom
 - [ ] Code the game of life
@@ -79,7 +86,7 @@ DONE:
     - chacha20
     - matrix computation
 - [X] Dev some basic commands
-    - [X] must use argc argv 
+    - [X] must use argc argv
     - [X] sleep
     - [X] help
     - [X] reboot

rtl/friscv_div.sv

@@ -11,7 +11,7 @@
 // support signed division.
 //
 // TODO: Save bandwidth by avoiding moving back and forth IDLE/OP if valid is 
-// already asserted when divisin is finished
+// already asserted when division is finished
 // TODO: manage pow2 division with a simple mux
 // TODO: save computation time by check the first MSB to use different than 0
 //
@@ -114,7 +114,6 @@ module friscv_div
                     // if slave is ready, move to the next operation from IDLE state
                     if (o_ready) begin
                         computing <= 1'b0;
-                        i_ready <= 1'b1;
                         step_cnt <= {CWIDTH{1'b0}};
                     end
 
@@ -147,6 +146,7 @@ module friscv_div
                 else _divs <= divs;
 
                 o_valid <= 1'b0;
+                i_ready <= 1'b1;
                 step_cnt <= {CWIDTH{1'b0}};
 
                 // Complete ASAP if trying to divide by zero

test/apps/run.sh

@@ -19,7 +19,7 @@ TIMEOUT=0
 MIN_PC=65692
 
 # Don't drop VCD, to avoid storing GB of raw data
-NO_VCD=1
+NO_VCD=0
 
 # Enable UART link to the processor (platform only)
 INTERACTIVE=1

test/apps/tests/common/makefile

@@ -24,7 +24,7 @@ CFLAGS +=	-march=rv32im \
 			-I./ \
 			-mcmodel=medany \
 			-static \
-			-std=gnu99
+			-std=gnu99 \
 
 # -e_start: Specify that the program entry point is _start
 # -nostartfiles: Do not use the standard system startup files when linking