Draft: Add s-mode CLIC interrupt testcases

This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros. Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. This pull requires: riscv-software-src/riscv-config#169, riscv-software-src/riscof#106 riscv-software-src/riscv-isa-sim#1596 To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.: spike/spike_isa.yaml: ISA: RV32IMCZicsr_Zifencei_Ssclic Signed-off-by: Dan Smathers <[email protected]>
dansmathers · Feb 9, 2024 · 547805c · 547805c
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diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicdeleg-01.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicdeleg-01.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicmdisable-01.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicmdisable-01.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicmdisable-02.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicmdisable-02.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicmdisable-03.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicmdisable-03.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicnodeleg-01.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicnodeleg-01.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicorder-01.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicorder-01.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicorder-02.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicorder-02.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicorder-03.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicorder-03.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicorder-04.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicorder-04.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicprivorder-01.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicprivorder-01.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicprivorder-02.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicprivorder-02.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicprivorder-03.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicprivorder-03.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicsdisable-01.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicsdisable-01.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicsdisable-02.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicsdisable-02.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicsdisable-03.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicsdisable-03.S
diff --git a/riscv-test-suite/rv32i_m/Ssclic/src/sclicwfi-01.S b/riscv-test-suite/rv32i_m/Ssclic/src/sclicwfi-01.S