cpu: implement inter-processor interrupts

This change provides routines that enable one processor to send a message to one or other processors to perform work. Signed-off-by: Jon Lange <[email protected]>
coconut-svsm · Dec 21, 2024 · 5d94146 · 5d94146
1 parent 80629ec
commit 5d94146
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Showing 8 changed files with 708 additions and 10 deletions.
diff --git a/kernel/src/cpu/apic.rs b/kernel/src/cpu/apic.rs
@@ -33,7 +33,7 @@ const APIC_REGISTER_ICR: u64 = 0x830;
 const APIC_REGISTER_SELF_IPI: u64 = 0x83F;
 
 #[derive(Debug, PartialEq)]
-enum IcrDestFmt {
+pub enum IcrDestFmt {
     Dest = 0,
     OnlySelf = 1,
     AllWithSelf = 2,
@@ -55,7 +55,7 @@ impl IcrDestFmt {
 }
 
 #[derive(Debug, PartialEq)]
-enum IcrMessageType {
+pub enum IcrMessageType {
     Fixed = 0,
     Unknown = 3,
     Nmi = 4,
@@ -81,7 +81,7 @@ impl IcrMessageType {
 }
 
 #[bitfield(u64)]
-struct ApicIcr {
+pub struct ApicIcr {
     pub vector: u8,
     #[bits(3)]
     pub message_type: IcrMessageType,

diff --git a/kernel/src/cpu/idt/common.rs b/kernel/src/cpu/idt/common.rs
@@ -46,6 +46,7 @@ pub const VC_VECTOR: usize = 29;
 pub const SX_VECTOR: usize = 30;
 
 pub const INT_INJ_VECTOR: usize = 0x50;
+pub const IPI_VECTOR: usize = 0xE0;
 
 bitflags::bitflags! {
     /// Page fault error code flags.

diff --git a/kernel/src/cpu/idt/entry.S b/kernel/src/cpu/idt/entry.S
@@ -421,4 +421,7 @@ default_entry_no_ist	name=int80	handler=system_call		error_code=0	vector=0x80
 // Interrupt injection vector
 irq_entry	name=int_inj	vector=0x50
 
+// IPI vector.
+irq_entry	name=ipi	vector=0xE0
+
 .popsection
diff --git a/kernel/src/cpu/idt/svsm.rs b/kernel/src/cpu/idt/svsm.rs
@@ -11,9 +11,9 @@ use super::super::tss::IST_DF;
 use super::super::vc::handle_vc_exception;
 use super::common::{
     idt_mut, user_mode, IdtEntry, IdtEventType, PageFaultError, AC_VECTOR, BP_VECTOR, BR_VECTOR,
-    CP_VECTOR, DB_VECTOR, DE_VECTOR, DF_VECTOR, GP_VECTOR, HV_VECTOR, INT_INJ_VECTOR, MCE_VECTOR,
-    MF_VECTOR, NMI_VECTOR, NM_VECTOR, NP_VECTOR, OF_VECTOR, PF_VECTOR, SS_VECTOR, SX_VECTOR,
-    TS_VECTOR, UD_VECTOR, VC_VECTOR, XF_VECTOR,
+    CP_VECTOR, DB_VECTOR, DE_VECTOR, DF_VECTOR, GP_VECTOR, HV_VECTOR, INT_INJ_VECTOR, IPI_VECTOR,
+    MCE_VECTOR, MF_VECTOR, NMI_VECTOR, NM_VECTOR, NP_VECTOR, OF_VECTOR, PF_VECTOR, SS_VECTOR,
+    SX_VECTOR, TS_VECTOR, UD_VECTOR, VC_VECTOR, XF_VECTOR,
 };
 use crate::address::VirtAddr;
 use crate::cpu::irq_state::{raw_get_tpr, raw_set_tpr, tpr_from_vector};
@@ -56,6 +56,7 @@ extern "C" {
     fn asm_entry_sx();
     fn asm_entry_int80();
     fn asm_entry_irq_int_inj();
+    fn asm_entry_irq_ipi();
 
     pub static mut HV_DOORBELL_ADDR: usize;
 }
@@ -92,6 +93,7 @@ pub fn early_idt_init() {
 
     // Interupts
     idt.set_entry(0x80, IdtEntry::user_entry(asm_entry_int80));
+    idt.set_entry(IPI_VECTOR, IdtEntry::entry(asm_entry_irq_ipi));
 
     // Load IDT
     idt.load();
@@ -363,9 +365,14 @@ pub fn common_isr_handler(vector: usize) {
     let cpu = this_cpu();
     cpu.irqs_enable();
 
-    // Treat any unhandled interrupt as a spurious interrupt.  Interrupt
-    // injection requests currently require no processing; they occur simply
-    // to ensure an exit from the guest.
+    // Process the requested interrupt vector.
+    match vector {
+        IPI_VECTOR => this_cpu().handle_ipi_interrupt(),
+        _ => {
+            // Ignore all unrecognized interrupt vectors and treat them as
+            // spurious interrupts.
+        }
+    }
 
     // Disable interrupts before restoring TPR.
     cpu.irqs_disable();