This is an interactive test bench for a simple VHDL adder. It uses GHDL to elaborate/run the simulation. It is coded in Python using the Cocotb library to implement the GUI test bench as a VPI plugin and pygame to render the GUI.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
generic (
DATA_WIDTH : positive := 4);
port (
A : in unsigned(DATA_WIDTH-1 downto 0);
B : in unsigned(DATA_WIDTH-1 downto 0);
X : out unsigned(DATA_WIDTH downto 0));
end entity adder;
architecture rtl of adder is
begin
add_proc : process (A, B) is
begin
X <= resize(A, X'length) + B;
end process add_proc;
end architecture rtl;
- Python (tested using version 3.9)
- GHDL Simulator
- GNU Make (build-essential package on *nix)
- Get Python dependencies first...
pip install -r requirements.txt
- Then in the test directory...
make
Sorry, but I need to create a docker image and instructions...
Many thanks to the GHDL VPI virtual board project for the inspiration and the images (which I shamelessly borrowed given how artistically challenged I am).