Update dev with master #3712
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Update dev with master #3712
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Sync dev to master
There is a naming conflict of the ALU module which prevents a successful synthesis with Yosys. This patch fixes this conflict. In addition, this patch introduces the configurations expected by Litex when generating an SoC This patch also adds a generator for System Verilog which works with Yosys
Add approved RocketChip technical charter to the project repository.
Add RocketChip Technical Charter
…x_issue3695 Rocket Core Clock Gate Bug Fix
Vector mask logical instructions are always unmasked, so there are no inactive elements, and the encodings with vm=0 are reserved.
fix `hartReset` in DM
fix BitPat for Vector Mask-Register Logical Instructions
ADD: Timing-Accurate Core Instruction Tracing
Fix DMCONTROLNxt naming
Update master with dev
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Related issue:
Type of change: bug report | feature request | other enhancement
Impact: no functional change | API addition (no impact on existing code) | API modification
Development Phase: proposal | implementation
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