Add initial DCLS support and documentation #354
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Coverage report for this PR is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/354/coverage_dashboard/all, documentation is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/354/docs_rendered/html |
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Coverage report for this PR is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/354/coverage_dashboard/all, documentation is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/354/docs_rendered/html |
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Coverage report for this PR is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/354/coverage_dashboard/all, documentation is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/354/docs_rendered/html |
Internal-tag: [#62496] Signed-off-by: Michal Czyz <[email protected]> Signed-off-by: Wiktoria Kuna <[email protected]>
Internal-tag: [#66891] Signed-off-by: Wiktoria Kuna <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
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Coverage report for this PR is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/354/coverage_dashboard/all, documentation is available at https://chipsalliance.github.io/Cores-VeeR-EL2//html/dev/354/docs_rendered/html |
This PR adds a Dual Core Lockstep feature into VeeR CPU behind configuration options. The DCLS tracks inputs and outputs of the main CPU core and compares it with the expected states. There is a possibility to include and track copy of the register file in a shadow core. New feature is configurable via following flags:
-set lockstep_enable=1that generatesRV_LOCKSTEP_ENABLEwhich enables the DCLS feature,-set lockstep_delay=<2-4>that generatesRV_LOCKSTEP_DELAYwhich specifies the delay between the shadow core and the main core,-set lockstep_regfile_enable=1that generatesRV_LOCKSTEP_REGFILE_ENABLEwhich exposes the register file to top level and adds it to the equvalency checker.The Dual Core Lockstep is appended to the documentation and comes with a test for delayed reset functionality.