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BLADE Example Designs

This repository contains a collection of example designs for getting started with BLADE. Before you start exploring these, make sure you have BLADE, DesignFormat and BLADE Templating on your system so that you can generate the RTL successfully.

Included Designs

The list of included designs is short at the moment, this will be expanded over time:

• design/basic_timer - A full tutorial on how to build a design with BLADE from scratch, including example code.
• designs/counter - A multi-channel timer demonstrating hierarchy, register blocks, wiring and Verilog templating.

Getting Started

System Requirements

You will need to fully setup BLADE, as well as installing some unique dependencies for simulation:

• BLADE - The core of BLADE
• DesignFormat - Design interchange format (BLADE's output format)
• BLADE Templating - Templating engine based on Mako
• Icarus Verilog - Opensource Verilog simulator
• GTKWave - Opensource VCD wave viewer

Generating and Simulating Designs

For most of the designs contained within this repository, Makefiles are provided to drive the generation and simulation flow. These designs support the following targets:

• make generate - Executes BLADE and BLADE Templating to generate hardware using templates
• make run - Builds the design and runs the simulation using Icarus Verilog
• make view - Opens the VCD trace file using GTKWave
• make clean - Deletes any artefacts created by generation or simulation leaving the source files intact

NOTE: This excludes the basic_timer design - instead you should read the tutorial to see the raw commands for generation and simulation.