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fix(riscv): add low order bits to faulting address #332

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fix(riscv): add low order bits to faulting address

fix(riscv): add low order bits to faulting address #332

Workflow file for this run

.github/workflows/build-riscv.yaml at 9bfb820
name: RISC-V Build
on:
push:
branches: [ main ]
pull_request:
workflow_dispatch:
jobs:
build-riscv:
runs-on: ubuntu-latest
container: baoproject/bao:latest
strategy:
matrix:
platform: [
"qemu-riscv64-virt",
]
irqc: [
"PLIC",
"APLIC",
"AIA",
]
ipic: [
"IPIC_SBI",
"IPIC_ACLINT",
]
cross_compile: [
"",
"CROSS_COMPILE=clang",
]
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- run: make PLATFORM=${{ matrix.platform }} IRQC=${{ matrix.irqc }} \
IPIC=${{ matrix.ipic }} CONFIG=null ${{ matrix.cross_compile }}