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Add tilegx over v9.2.111 #408

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Add tilegx over v9.2.111 #408

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fd6bf76
Update version to 9.2.111 [ci skip]
github-actions[bot] Jul 16, 2024
73be02b
pyvex: Add TILEGX to arches
shaymargolis Jul 16, 2024
d06588c
pyvex_c: Allow VexArchTILEGX lifting
shaymargolis Jul 16, 2024
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4 changes: 3 additions & 1 deletion pyvex/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
For an introduction to VEX, take a look here: https://docs.angr.io/advanced-topics/ir
"""

__version__ = "9.2.111.dev0"
__version__ = "9.2.111"

from . import const, expr, stmt
from .arches import (
Expand All @@ -23,6 +23,7 @@
ARCH_RISCV64_LE,
ARCH_S390X,
ARCH_X86,
ARCH_TILEGX,
)
from .block import IRSB, IRTypeEnv
from .const import get_type_size, get_type_spec_size, tag_to_const_class
Expand Down Expand Up @@ -89,4 +90,5 @@
"ARCH_MIPS64_BE",
"ARCH_MIPS64_LE",
"ARCH_RISCV64_LE",
"ARCH_TILEGX",
]
3 changes: 3 additions & 0 deletions pyvex/arches.py
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Expand Up @@ -28,6 +28,7 @@ def __init__(self, name: str, bits: int, memory_endness: str, instruction_endnes
"MIPS32": "VexArchMIPS32",
"MIPS64": "VexArchMIPS64",
"RISCV64": "VexArchRISCV64",
"TILEGX": "VexArchTILEGX",
}[name]
self.ip_offset = guest_offsets[
(
Expand All @@ -43,6 +44,7 @@ def __init__(self, name: str, bits: int, memory_endness: str, instruction_endnes
"MIPS32": "pc",
"MIPS64": "pc",
"RISCV64": "pc",
"TILEGX": "pc",
}[name],
)
]
Expand Down Expand Up @@ -92,3 +94,4 @@ def get_register_offset(self, name: str) -> int:
ARCH_MIPS64_BE = PyvexArch("MIPS64", 64, "Iend_BE")
ARCH_MIPS64_LE = PyvexArch("MIPS64", 64, "Iend_LE")
ARCH_RISCV64_LE = PyvexArch("RISCV64", 64, "Iend_LE", instruction_endness="Iend_LE")
ARCH_TILEGX = PyvexArch("TILEGX", 64, "Iend_LE")
1 change: 1 addition & 0 deletions pyvex/lifting/libvex.py
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Expand Up @@ -26,6 +26,7 @@
"PPC64",
"S390X",
"RISCV64",
"TILEGX"
}

VEX_MAX_INSTRUCTIONS = 99
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3 changes: 3 additions & 0 deletions pyvex_c/pyvex.c
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Expand Up @@ -279,6 +279,9 @@ static void vex_prepare_vai(VexArch arch, VexArchInfo *vai) {
case VexArchRISCV64:
vai->hwcaps = 0;
break;
case VexArchTILEGX:
vai->hwcaps = 0;
break;
default:
pyvex_error("Invalid arch in vex_prepare_vai.\n");
break;
Expand Down