tmp: Intermediary commit to fix interconnect build issue

analogdevicesinc · Jan 22, 2025 · 9dae66d · 9dae66d
1 parent 74d3103
commit 9dae66d
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Showing 4 changed files with 6 additions and 6 deletions.
diff --git a/CI/scripts_hdl/matlab_processors.tcl b/CI/scripts_hdl/matlab_processors.tcl
@@ -47,9 +47,9 @@ proc preprocess_bd {project carrier rxtx} {
 	    }
 	  switch $carrier {
           zed {
-                set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
-                connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
-                connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
+                set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_gp0_interconnect]
+                connect_bd_net [get_bd_pins axi_gp0_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
+                connect_bd_net [get_bd_pins axi_gp0_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
               }
           }
         }

diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m b/hdl/vendor/AnalogDevices/+AnalogDevices/get_memory_axi_interface_info.m
@@ -5,7 +5,7 @@
    case 'cn0585'
         switch fpga
             case{'ZED'}
-                InterfaceConnection = 'axi_cpu_interconnect/M20_AXI';
+                InterfaceConnection = 'axi_gp0_interconnect/M20_AXI';
                 BaseAddress = '0x43C00000';
                 MasterAddressSpace = 'sys_ps7/Data';
             otherwise

diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m
@@ -20,7 +20,7 @@
 hRD.BoardName = sprintf('AnalogDevices %s %s', pname, upper(board));
 
 % Tool information
-hRD.SupportedToolVersion = {'2022.2'};
+hRD.SupportedToolVersion = {'2023.2'};
 
 % Get the root directory
 rootDir = fileparts(strtok(mfilename('fullpath'), '+'));

diff --git a/...targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m b/...targeting/cn0585/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+zed/+tx/add_tx_io.m
@@ -2,7 +2,7 @@ function add_tx_io(hRD)
 
 % add AXI4 and AXI4-Lite slave interfaces
 hRD.addAXI4SlaveInterface( ...
-    'InterfaceConnection', 'axi_cpu_interconnect/M20_AXI', ...
+    'InterfaceConnection', 'axi_gp0_interconnect/M20_AXI', ...
     'BaseAddress',         '0x43C00000', ...
     'MasterAddressSpace',  'sys_ps7/Data');