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Create phys nets from logical #770

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22c4885
Created parameterizable counter with an adder as a submodule
haydenc-amd Jun 16, 2023
3f246d6
Merge branch 'master' of github.com:Xilinx/RapidWright
haydenc-amd Jun 20, 2023
b0e02c5
Merge branch 'master' of github.com:Xilinx/RapidWright
haydenc-amd Jul 26, 2023
2c26582
added function that creates physical nets from a finalized logical ne…
haydenc-amd Jul 26, 2023
bb3d253
added return to the javadoc string for createPhysNetFromLogical()
haydenc-amd Jul 26, 2023
f9b2ba7
Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
3998094
Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
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Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
76f0a47
Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
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Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
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Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
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Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
7468f01
Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
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Update src/com/xilinx/rapidwright/design/DesignTools.java
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Update src/com/xilinx/rapidwright/design/DesignTools.java
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Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
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Update src/com/xilinx/rapidwright/design/DesignTools.java
haydenc-amd Aug 16, 2023
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haydenc-amd Aug 16, 2023
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haydenc-amd Aug 17, 2023
6b65825
createPhysNetFromLogical() now works with GND and VCC nets
haydenc-amd Aug 21, 2023
a407611
Merge branch 'master' into createPhysNetsFromLogical
clavin-xlnx Aug 31, 2023
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102 changes: 102 additions & 0 deletions src/com/xilinx/rapidwright/design/DesignTools.java
Original file line number Diff line number Diff line change
Expand Up @@ -3963,6 +3963,108 @@ public static void updatePinsIsRouted(Net net) {
}

/**
* Creates physical nets from all the logical EDIF nets. Assumes that the EDIF netlist is finalized.
* @param d The design that contains the complete logical netlist and where the physical nets will be created.
*/
public static void createPhysNetsFromLogical(Design d) {
EDIFNet gnd = EDIFTools.getStaticNet(NetType.GND, d.getTopEDIFCell(), d.getNetlist());
EDIFNet vcc = EDIFTools.getStaticNet(NetType.VCC, d.getTopEDIFCell(), d.getNetlist());

// Iterate through all canonical nets
Map<EDIFHierNet, EDIFHierNet> parentNetMap = d.getNetlist().getParentNetMap();
for (EDIFHierNet n : parentNetMap.values()) {
// if (n.getNet().equals(gnd) || n.getNet().equals(vcc)) continue; // Static nets do not have physical equivalents
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createPhysNetFromLogical(d, n);
}
}

/**
* Creates a physical nets from the provided logical EDIF net. Assumes that the EDIF netlist is finalized.
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* @param d The design that contains the complete logical netlist and where the physical net will be created.
* @param edifNet The EDIF Net to create into a physical net.
* @return A list of the SitePinInsts added to the newly created physical net
*/
public static List<SitePinInst> createPhysNetFromLogical(Design d, EDIFHierNet edifNet) {
//check whether net already exists
if (d.getNet(edifNet.getHierarchicalNetName()) != null) return null;

Net net; //create physical net
if(edifNet.getNet().equals(EDIFTools.getStaticNet(NetType.GND, d.getTopEDIFCell(), d.getNetlist())))
net = d.getGndNet();
else if(edifNet.getNet().equals(EDIFTools.getStaticNet(NetType.VCC, d.getTopEDIFCell(), d.getNetlist())))
net = d.getVccNet();
else
net = d.createNet(edifNet);
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// Get source EDIF port inst
EDIFHierPortInst srcPort = null;
for (EDIFHierPortInst hierPortInst : d.getNetlist().getPhysicalPins(edifNet)) {
EDIFPortInst portInst = hierPortInst.getPortInst();
if (portInst.isOutput() && portInst.getCellInst() != null) {
srcPort = hierPortInst;
break;
}
}

// Get cell connected to port inst
Cell srcCell = d.getCell(srcPort.getFullHierarchicalInstName());

// Connect physical net to the physical cell pins corresponding to the logical ports
List<SitePinInst> sitePins = new ArrayList<>();
for(EDIFHierPortInst hierPortInst: d.getNetlist().getPhysicalPins(edifNet)) {
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EDIFPortInst portInst = hierPortInst.getPortInst();
if (portInst.equals(srcPort)) continue;

EDIFCellInst cellInst = portInst.getCellInst();
Cell cell = cellInst == null ? null : d.getCell(cellInst.getName());
if (cell == null) continue;

// Only create connection if the net goes outside the site. This prevents sitePins instances from
// erroneously being created.
if (!isIntraSiteConnection(srcCell, srcPort.getPortInst(), cell, portInst))
sitePins.add(net.connect(cell, portInst.getName()));
}

if (srcCell != null && sitePins.size() > 0) {
net.connect(srcCell, srcPort.getPortInst().getName());
}

return sitePins;
}

/**
* Checks if the two provided ports of two cells can be connected without leaving the site.
* @param srcCell source cell
* @param srcPort port of source Cell
* @param dstCell destination cell
* @param dstPort port of destination cell
* @return true if the ports can be connected without leaving the site. False otherwise.
*/
public static boolean isIntraSiteConnection(Cell srcCell, EDIFPortInst srcPort, Cell dstCell, EDIFPortInst dstPort) {
if (dstCell.getSite().equals(srcCell.getSite())) {
Queue<BELPin> queue = new LinkedList<>();
queue.add(srcCell.getBELPin(srcPort));
BELPin dstPin = dstCell.getBELPin(dstPort);
while (!queue.isEmpty()) {
ArrayList<BELPin> conns = queue.poll().getSiteConns();
for (BELPin pin : conns) {
if (pin.equals(dstPin)) {
return true;
}
else if (pin.isInput() && pin.getBEL().getBELClass() == BELClass.RBEL) {
for (BELPin nextPin : pin.getBEL().getPins()) {
if (nextPin.isOutput()) {
queue.add(nextPin);
}
}
}
}
}
}
return false;
}

/*
* Update the SitePinInst.isRouted() value of all sink pins in the given
* Design. See {@link #updatePinsIsRouted(Net)}.
* @param design Design in which pins are to be updated.
Expand Down